Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 3 | * |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 5 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 6f57b51 | 2010-07-08 16:41:05 +0000 | [diff] [blame] | 17 | |
| 18 | #if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 19 | static void print_tx(const char *strval, u32 val) |
| 20 | { |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 21 | #if CONFIG_DEBUG_RAM_SETUP |
Myles Watson | 362db61 | 2010-04-08 15:12:18 +0000 | [diff] [blame] | 22 | printk(BIOS_DEBUG, "%s%08x\n", strval, val); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 23 | #endif |
| 24 | } |
| 25 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 26 | static void print_t(const char *strval) |
| 27 | { |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 28 | #if CONFIG_DEBUG_RAM_SETUP |
Myles Watson | 362db61 | 2010-04-08 15:12:18 +0000 | [diff] [blame] | 29 | printk(BIOS_DEBUG, "%s", strval); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 30 | #endif |
| 31 | } |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 32 | #endif |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 33 | |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 34 | static void print_tf(const char *func, const char *strval) |
| 35 | { |
| 36 | #if CONFIG_DEBUG_RAM_SETUP |
| 37 | printk(BIOS_DEBUG, "%s: %s", func, strval); |
| 38 | #endif |
| 39 | } |
| 40 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 41 | static inline void fam15h_switch_dct(uint32_t dev, uint8_t dct) |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 42 | { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 43 | uint32_t dword; |
| 44 | |
| 45 | dword = Get_NB32(dev, 0x10c); |
| 46 | dword &= ~0x1; |
| 47 | dword |= (dct & 0x1); |
| 48 | Set_NB32(dev, 0x10c, dword); |
| 49 | } |
| 50 | |
| 51 | static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_pstate) |
| 52 | { |
| 53 | uint32_t dword; |
| 54 | |
| 55 | dword = Get_NB32(dev, 0x10c); |
| 56 | dword &= ~(0x3 << 4); |
| 57 | dword |= (nb_pstate & 0x3) << 4; |
| 58 | Set_NB32(dev, 0x10c, dword); |
| 59 | } |
| 60 | |
| 61 | static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) |
| 62 | { |
| 63 | if (is_fam15h()) { |
| 64 | /* Obtain address of function 0x1 */ |
| 65 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 66 | fam15h_switch_dct(dev_map, dct); |
| 67 | return Get_NB32(dev, reg); |
| 68 | } else { |
| 69 | return Get_NB32(dev, (0x100 * dct) + reg); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val) |
| 74 | { |
| 75 | if (is_fam15h()) { |
| 76 | /* Obtain address of function 0x1 */ |
| 77 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 78 | fam15h_switch_dct(dev_map, dct); |
| 79 | Set_NB32(dev, reg, val); |
| 80 | } else { |
| 81 | Set_NB32(dev, (0x100 * dct) + reg, val); |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg) |
| 86 | { |
| 87 | if (is_fam15h()) { |
| 88 | /* Obtain address of function 0x1 */ |
| 89 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 90 | fam15h_switch_dct(dev_map, dct); |
| 91 | fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); |
| 92 | return Get_NB32(dev, reg); |
| 93 | } else { |
| 94 | return Get_NB32(dev, (0x100 * dct) + reg); |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val) |
| 99 | { |
| 100 | if (is_fam15h()) { |
| 101 | /* Obtain address of function 0x1 */ |
| 102 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 103 | fam15h_switch_dct(dev_map, dct); |
| 104 | fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); |
| 105 | Set_NB32(dev, reg, val); |
| 106 | } else { |
| 107 | Set_NB32(dev, (0x100 * dct) + reg, val); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index) |
| 112 | { |
| 113 | if (is_fam15h()) { |
| 114 | /* Obtain address of function 0x1 */ |
| 115 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 116 | fam15h_switch_dct(dev_map, dct); |
| 117 | return Get_NB32_index_wait(dev, index_reg, index); |
| 118 | } else { |
| 119 | return Get_NB32_index_wait(dev, (0x100 * dct) + index_reg, index); |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | static inline void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data) |
| 124 | { |
| 125 | if (is_fam15h()) { |
| 126 | /* Obtain address of function 0x1 */ |
| 127 | uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); |
| 128 | fam15h_switch_dct(dev_map, dct); |
| 129 | Set_NB32_index_wait(dev, index_reg, index, data); |
| 130 | } else { |
| 131 | Set_NB32_index_wait(dev, (0x100 * dct) + index_reg, index, data); |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | static uint16_t voltage_index_to_mv(uint8_t index) |
| 136 | { |
| 137 | if (index & 0x8) |
| 138 | return 1150; |
| 139 | if (index & 0x4) |
| 140 | return 1250; |
| 141 | else if (index & 0x2) |
| 142 | return 1350; |
| 143 | else |
| 144 | return 1500; |
| 145 | } |
| 146 | |
| 147 | static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) |
| 148 | { |
| 149 | /* FIXME |
| 150 | * Mainboards need to be able to specify the maximum number of DIMMs installable per channel |
| 151 | * For now assume a maximum of 2 DIMMs per channel can be installed |
| 152 | */ |
| 153 | uint8_t MaxDimmsInstallable = 2; |
| 154 | |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 155 | /* Return limited maximum RAM frequency */ |
| 156 | if (IS_ENABLED(CONFIG_DIMM_DDR2)) { |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 157 | if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 158 | /* K10 BKDG Rev. 3.62 Table 53 */ |
| 159 | if (count > 2) { |
| 160 | /* Limit to DDR2-533 */ |
| 161 | if (freq > 266) { |
| 162 | freq = 266; |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 163 | print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n"); |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 164 | } |
| 165 | } |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 166 | } else { |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 167 | /* K10 BKDG Rev. 3.62 Table 52 */ |
| 168 | if (count > 1) { |
| 169 | /* Limit to DDR2-800 */ |
| 170 | if (freq > 400) { |
| 171 | freq = 400; |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 172 | print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n"); |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 173 | } |
| 174 | } |
| 175 | } |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 176 | } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 177 | if (voltage == 0) { |
| 178 | printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); |
| 179 | voltage = 0x1; |
| 180 | } |
| 181 | |
| 182 | if (is_fam15h()) { |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 183 | if (CONFIG_CPU_SOCKET_TYPE == 0x15) { |
| 184 | /* Socket G34 */ |
| 185 | if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { |
| 186 | /* Fam15h BKDG Rev. 3.14 Table 27 */ |
| 187 | if (voltage & 0x4) { |
| 188 | /* 1.25V */ |
| 189 | if (count > 1) { |
| 190 | if (highest_rank_count > 1) { |
| 191 | /* Limit to DDR3-1066 */ |
| 192 | if (freq > 533) { |
| 193 | freq = 533; |
| 194 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 195 | } |
| 196 | } else { |
| 197 | /* Limit to DDR3-1333 */ |
| 198 | if (freq > 666) { |
| 199 | freq = 666; |
| 200 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 201 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 202 | } |
| 203 | } else { |
| 204 | /* Limit to DDR3-1333 */ |
| 205 | if (freq > 666) { |
| 206 | freq = 666; |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 207 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 208 | } |
| 209 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 210 | } else if (voltage & 0x2) { |
| 211 | /* 1.35V */ |
| 212 | if (count > 1) { |
| 213 | /* Limit to DDR3-1333 */ |
| 214 | if (freq > 666) { |
| 215 | freq = 666; |
| 216 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 217 | } |
| 218 | } else { |
| 219 | /* Limit to DDR3-1600 */ |
| 220 | if (freq > 800) { |
| 221 | freq = 800; |
| 222 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 223 | } |
| 224 | } |
| 225 | } else if (voltage & 0x1) { |
| 226 | /* 1.50V */ |
| 227 | if (count > 1) { |
| 228 | /* Limit to DDR3-1600 */ |
| 229 | if (freq > 800) { |
| 230 | freq = 800; |
| 231 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 232 | } |
| 233 | } else { |
| 234 | /* Limit to DDR3-1866 */ |
| 235 | if (freq > 933) { |
| 236 | freq = 933; |
| 237 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); |
| 238 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 239 | } |
| 240 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 241 | } else { |
| 242 | /* Fam15h BKDG Rev. 3.14 Table 26 */ |
| 243 | if (voltage & 0x4) { |
| 244 | /* 1.25V */ |
| 245 | if (count > 1) { |
| 246 | if (highest_rank_count > 1) { |
| 247 | /* Limit to DDR3-1066 */ |
| 248 | if (freq > 533) { |
| 249 | freq = 533; |
| 250 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 251 | } |
| 252 | } else { |
| 253 | /* Limit to DDR3-1333 */ |
| 254 | if (freq > 666) { |
| 255 | freq = 666; |
| 256 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 257 | } |
| 258 | } |
| 259 | } else { |
| 260 | /* Limit to DDR3-1333 */ |
| 261 | if (freq > 666) { |
| 262 | freq = 666; |
| 263 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 264 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 265 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 266 | } else if (voltage & 0x2) { |
| 267 | /* 1.35V */ |
| 268 | if (MaxDimmsInstallable > 1) { |
| 269 | /* Limit to DDR3-1333 */ |
| 270 | if (freq > 666) { |
| 271 | freq = 666; |
| 272 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 273 | } |
| 274 | } else { |
| 275 | /* Limit to DDR3-1600 */ |
| 276 | if (freq > 800) { |
| 277 | freq = 800; |
| 278 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 279 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 280 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 281 | } else if (voltage & 0x1) { |
| 282 | if (MaxDimmsInstallable == 1) { |
| 283 | if (count > 1) { |
| 284 | /* Limit to DDR3-1600 */ |
| 285 | if (freq > 800) { |
| 286 | freq = 800; |
| 287 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 288 | } |
| 289 | } else { |
| 290 | /* Limit to DDR3-1866 */ |
| 291 | if (freq > 933) { |
| 292 | freq = 933; |
| 293 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); |
| 294 | } |
| 295 | } |
| 296 | } else { |
| 297 | if (count > 1) { |
| 298 | if (highest_rank_count > 1) { |
| 299 | /* Limit to DDR3-1333 */ |
| 300 | if (freq > 666) { |
| 301 | freq = 666; |
| 302 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 303 | } |
| 304 | } else { |
| 305 | /* Limit to DDR3-1600 */ |
| 306 | if (freq > 800) { |
| 307 | freq = 800; |
| 308 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 309 | } |
| 310 | } |
| 311 | } else { |
| 312 | /* Limit to DDR3-1600 */ |
| 313 | if (freq > 800) { |
| 314 | freq = 800; |
| 315 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 316 | } |
| 317 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 318 | } |
| 319 | } |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 320 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 321 | } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { |
| 322 | /* Socket C32 */ |
| 323 | if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { |
| 324 | /* Fam15h BKDG Rev. 3.14 Table 30 */ |
| 325 | if (voltage & 0x4) { |
| 326 | /* 1.25V */ |
| 327 | if (count > 1) { |
| 328 | if (highest_rank_count > 2) { |
| 329 | /* Limit to DDR3-800 */ |
| 330 | if (freq > 400) { |
| 331 | freq = 400; |
| 332 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); |
| 333 | } |
| 334 | } else { |
| 335 | /* Limit to DDR3-1333 */ |
| 336 | if (freq > 666) { |
| 337 | freq = 666; |
| 338 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 339 | } |
| 340 | } |
| 341 | } else { |
| 342 | /* Limit to DDR3-1333 */ |
| 343 | if (freq > 666) { |
| 344 | freq = 666; |
| 345 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 346 | } |
| 347 | } |
| 348 | } else if (voltage & 0x2) { |
| 349 | /* 1.35V */ |
| 350 | if (count > 1) { |
| 351 | if (highest_rank_count > 2) { |
| 352 | /* Limit to DDR3-800 */ |
| 353 | if (freq > 400) { |
| 354 | freq = 400; |
| 355 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); |
| 356 | } |
| 357 | } else if (highest_rank_count > 1) { |
| 358 | /* Limit to DDR3-1066 */ |
| 359 | if (freq > 533) { |
| 360 | freq = 533; |
| 361 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 362 | } |
| 363 | } else { |
| 364 | /* Limit to DDR3-1333 */ |
| 365 | if (freq > 666) { |
| 366 | freq = 666; |
| 367 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 368 | } |
| 369 | } |
| 370 | } else { |
| 371 | /* Limit to DDR3-1600 */ |
| 372 | if (freq > 800) { |
| 373 | freq = 800; |
| 374 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 375 | } |
| 376 | } |
| 377 | } else if (voltage & 0x1) { |
| 378 | /* 1.50V */ |
| 379 | if (count > 1) { |
| 380 | if (highest_rank_count > 2) { |
| 381 | /* Limit to DDR3-800 */ |
| 382 | if (freq > 400) { |
| 383 | freq = 400; |
| 384 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); |
| 385 | } |
| 386 | } else if (highest_rank_count > 1) { |
| 387 | /* Limit to DDR3-1066 */ |
| 388 | if (freq > 533) { |
| 389 | freq = 533; |
| 390 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 391 | } |
| 392 | } else { |
| 393 | /* Limit to DDR3-1333 */ |
| 394 | if (freq > 666) { |
| 395 | freq = 666; |
| 396 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 397 | } |
| 398 | } |
| 399 | } else { |
| 400 | if (highest_rank_count > 2) { |
| 401 | /* Limit to DDR3-1333 */ |
| 402 | if (freq > 666) { |
| 403 | freq = 666; |
| 404 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 405 | } |
| 406 | } else { |
| 407 | /* Limit to DDR3-1600 */ |
| 408 | if (freq > 800) { |
| 409 | freq = 800; |
| 410 | printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 411 | } |
| 412 | } |
| 413 | } |
| 414 | } |
| 415 | } else { |
| 416 | /* Fam15h BKDG Rev. 3.14 Table 29 */ |
| 417 | if (voltage & 0x4) { |
| 418 | /* 1.25V */ |
| 419 | if (count > 1) { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 420 | /* Limit to DDR3-1066 */ |
| 421 | if (freq > 533) { |
| 422 | freq = 533; |
| 423 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 424 | } |
| 425 | } else { |
| 426 | /* Limit to DDR3-1333 */ |
| 427 | if (freq > 666) { |
| 428 | freq = 666; |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 429 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 430 | } |
| 431 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 432 | } else if (voltage & 0x2) { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 433 | if (count > 1) { |
| 434 | if (highest_rank_count > 1) { |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 435 | /* Limit to DDR3-1066 */ |
| 436 | if (freq > 533) { |
| 437 | freq = 533; |
| 438 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 439 | } |
| 440 | } else { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 441 | /* Limit to DDR3-1333 */ |
| 442 | if (freq > 666) { |
| 443 | freq = 666; |
| 444 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 445 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 446 | } |
| 447 | } else { |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 448 | /* Limit to DDR3-1333 */ |
| 449 | if (freq > 666) { |
| 450 | freq = 666; |
| 451 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 452 | } |
| 453 | } |
| 454 | } else if (voltage & 0x1) { |
| 455 | if (MaxDimmsInstallable == 1) { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 456 | /* Limit to DDR3-1600 */ |
| 457 | if (freq > 800) { |
| 458 | freq = 800; |
| 459 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 460 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 461 | } else { |
| 462 | if (count > 1) { |
| 463 | if (highest_rank_count > 1) { |
| 464 | /* Limit to DDR3-1066 */ |
| 465 | if (freq > 533) { |
| 466 | freq = 533; |
| 467 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 468 | } |
| 469 | } else { |
| 470 | /* Limit to DDR3-1333 */ |
| 471 | if (freq > 666) { |
| 472 | freq = 666; |
| 473 | printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 474 | } |
| 475 | } |
| 476 | } else { |
| 477 | /* Limit to DDR3-1600 */ |
| 478 | if (freq > 800) { |
| 479 | freq = 800; |
| 480 | printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); |
| 481 | } |
| 482 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 483 | } |
| 484 | } |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 485 | } |
Timothy Pearson | 19ce16a | 2015-11-24 14:11:47 -0600 | [diff] [blame] | 486 | } else { |
| 487 | /* TODO |
| 488 | * Other socket support unimplemented |
| 489 | */ |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 490 | } |
| 491 | } else { |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 492 | if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { |
| 493 | /* K10 BKDG Rev. 3.62 Table 34 */ |
| 494 | if (count > 2) { |
| 495 | /* Limit to DDR3-800 */ |
| 496 | if (freq > 400) { |
| 497 | freq = 400; |
| 498 | printk(BIOS_DEBUG, "%s: More than 2 registered DIMMs on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); |
| 499 | } |
| 500 | } else if (count == 2) { |
| 501 | /* Limit to DDR3-1066 */ |
| 502 | if (freq > 533) { |
| 503 | freq = 533; |
| 504 | printk(BIOS_DEBUG, "%s: 2 registered DIMMs on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); |
| 505 | } |
| 506 | } else { |
| 507 | /* Limit to DDR3-1333 */ |
| 508 | if (freq > 666) { |
| 509 | freq = 666; |
| 510 | printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 511 | } |
| 512 | } |
| 513 | } else { |
| 514 | /* K10 BKDG Rev. 3.62 Table 33 */ |
| 515 | /* Limit to DDR3-1333 */ |
| 516 | if (freq > 666) { |
| 517 | freq = 666; |
| 518 | printk(BIOS_DEBUG, "%s: unbuffered DIMMs on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); |
| 519 | } |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 520 | } |
| 521 | } |
Timothy Pearson | 3c20678 | 2015-02-14 03:32:21 -0600 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | return freq; |
| 525 | } |
| 526 | |
Elyes HAOUAS | 04f8fd9 | 2016-09-19 10:24:34 -0600 | [diff] [blame^] | 527 | #if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */ |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 528 | #include "amdfam10.h" |
| 529 | #include "../amdmct/wrappers/mcti.h" |
| 530 | #include "../amdmct/amddefs.h" |
| 531 | #include "../amdmct/mct_ddr3/mwlc_d.h" |
| 532 | #include "../amdmct/mct_ddr3/mct_d.h" |
| 533 | #include "../amdmct/mct_ddr3/mct_d_gcc.h" |
| 534 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 535 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
| 536 | #include "../amdmct/mct_ddr3/s3utils.c" |
| 537 | #endif |
| 538 | |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 539 | #include "../amdmct/wrappers/mcti_d.c" |
| 540 | #include "../amdmct/mct_ddr3/mct_d.c" |
| 541 | |
| 542 | #include "../amdmct/mct_ddr3/mctmtr_d.c" |
| 543 | #include "../amdmct/mct_ddr3/mctcsi_d.c" |
| 544 | #include "../amdmct/mct_ddr3/mctecc_d.c" |
| 545 | #include "../amdmct/mct_ddr3/mctdqs_d.c" |
| 546 | #include "../amdmct/mct_ddr3/mctsrc.c" |
| 547 | #include "../amdmct/mct_ddr3/mctsdi.c" |
Timothy Pearson | 4530df4 | 2015-08-02 21:23:02 -0500 | [diff] [blame] | 548 | #include "../amdmct/mct_ddr3/mctprod.c" |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 549 | #include "../amdmct/mct_ddr3/mctproc.c" |
| 550 | #include "../amdmct/mct_ddr3/mctprob.c" |
| 551 | #include "../amdmct/mct_ddr3/mcthwl.c" |
| 552 | #include "../amdmct/mct_ddr3/mctwl.c" |
| 553 | #include "../amdmct/mct_ddr3/mport_d.c" |
| 554 | #include "../amdmct/mct_ddr3/mutilc_d.c" |
| 555 | #include "../amdmct/mct_ddr3/modtrdim.c" |
| 556 | #include "../amdmct/mct_ddr3/mhwlc_d.c" |
| 557 | #include "../amdmct/mct_ddr3/mctrci.c" |
| 558 | #include "../amdmct/mct_ddr3/mctsrc1p.c" |
| 559 | #include "../amdmct/mct_ddr3/mcttmrl.c" |
| 560 | #include "../amdmct/mct_ddr3/mcthdi.c" |
| 561 | #include "../amdmct/mct_ddr3/mctndi_d.c" |
| 562 | #include "../amdmct/mct_ddr3/mctchi_d.c" |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 563 | #include "../amdmct/mct_ddr3/modtrd.c" |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 564 | |
| 565 | #if CONFIG_CPU_SOCKET_TYPE == 0x10 |
| 566 | //TODO: S1G1? |
| 567 | #elif CONFIG_CPU_SOCKET_TYPE == 0x11 |
| 568 | //AM3 |
| 569 | #include "../amdmct/mct_ddr3/mctardk5.c" |
| 570 | #elif CONFIG_CPU_SOCKET_TYPE == 0x12 |
| 571 | //F (1207), Fr2, G (1207) |
| 572 | #include "../amdmct/mct_ddr3/mctardk6.c" |
| 573 | #elif CONFIG_CPU_SOCKET_TYPE == 0x13 |
| 574 | //ASB2 |
| 575 | #include "../amdmct/mct_ddr3/mctardk5.c" |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 576 | //C32 |
| 577 | #elif CONFIG_CPU_SOCKET_TYPE == 0x14 |
| 578 | #include "../amdmct/mct_ddr3/mctardk5.c" |
Timothy Pearson | 99e1a67 | 2015-09-05 18:00:27 -0500 | [diff] [blame] | 579 | //G34 |
| 580 | #elif CONFIG_CPU_SOCKET_TYPE == 0x15 |
| 581 | #include "../amdmct/mct_ddr3/mctardk5.c" |
Damien Zammit | 33aaa92 | 2016-02-10 14:01:36 +1100 | [diff] [blame] | 582 | //FM2 |
| 583 | #elif CONFIG_CPU_SOCKET_TYPE == 0x16 |
| 584 | #include "../amdmct/mct_ddr3/mctardk5.c" |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 585 | #endif |
| 586 | |
| 587 | #else /* DDR2 */ |
| 588 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 589 | #include "amdfam10.h" |
| 590 | #include "../amdmct/wrappers/mcti.h" |
| 591 | #include "../amdmct/amddefs.h" |
| 592 | #include "../amdmct/mct/mct_d.h" |
| 593 | #include "../amdmct/mct/mct_d_gcc.h" |
| 594 | |
| 595 | #include "../amdmct/wrappers/mcti_d.c" |
| 596 | #include "../amdmct/mct/mct_d.c" |
| 597 | |
| 598 | |
| 599 | #include "../amdmct/mct/mctmtr_d.c" |
| 600 | #include "../amdmct/mct/mctcsi_d.c" |
| 601 | #include "../amdmct/mct/mctecc_d.c" |
| 602 | #include "../amdmct/mct/mctpro_d.c" |
| 603 | #include "../amdmct/mct/mctdqs_d.c" |
| 604 | #include "../amdmct/mct/mctsrc.c" |
| 605 | #include "../amdmct/mct/mctsrc1p.c" |
| 606 | #include "../amdmct/mct/mcttmrl.c" |
| 607 | #include "../amdmct/mct/mcthdi.c" |
| 608 | #include "../amdmct/mct/mctndi_d.c" |
| 609 | #include "../amdmct/mct/mctchi_d.c" |
| 610 | |
Zheng Bao | db8b411 | 2009-07-01 07:01:32 +0000 | [diff] [blame] | 611 | #if CONFIG_CPU_SOCKET_TYPE == 0x10 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 612 | //L1 |
| 613 | #include "../amdmct/mct/mctardk3.c" |
Zheng Bao | db8b411 | 2009-07-01 07:01:32 +0000 | [diff] [blame] | 614 | #elif CONFIG_CPU_SOCKET_TYPE == 0x11 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 615 | //AM2 |
| 616 | #include "../amdmct/mct/mctardk4.c" |
| 617 | //#elif SYSTEM_TYPE == MOBILE |
| 618 | //s1g1 |
| 619 | //#include "../amdmct/mct/mctardk5.c" |
| 620 | #endif |
| 621 | |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 622 | #endif /* DDR2 */ |
| 623 | |
Stefan Reinauer | fd4f413 | 2013-06-19 12:25:44 -0700 | [diff] [blame] | 624 | #include <arch/early_variables.h> |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 625 | struct sys_info sysinfo_car CAR_GLOBAL; |
| 626 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 627 | int mctRead_SPD(u32 smaddr, u32 reg) |
| 628 | { |
| 629 | return spd_read_byte(smaddr, reg); |
| 630 | } |
| 631 | |
| 632 | |
| 633 | void mctSMBhub_Init(u32 node) |
| 634 | { |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 635 | struct sys_info *sysinfo = &sysinfo_car; |
Elyes HAOUAS | 04f8fd9 | 2016-09-19 10:24:34 -0600 | [diff] [blame^] | 636 | struct mem_controller *ctrl = &(sysinfo->ctrl[node]); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 637 | activate_spd_rom(ctrl); |
| 638 | } |
| 639 | |
| 640 | |
| 641 | void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) |
| 642 | { |
| 643 | int j; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 644 | struct sys_info *sysinfo = &sysinfo_car; |
Elyes HAOUAS | 04f8fd9 | 2016-09-19 10:24:34 -0600 | [diff] [blame^] | 645 | struct mem_controller *ctrl = &(sysinfo->ctrl[node]); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 646 | |
Elyes HAOUAS | 04f8fd9 | 2016-09-19 10:24:34 -0600 | [diff] [blame^] | 647 | for (j = 0; j < DIMM_SOCKETS; j++) { |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 648 | pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; |
| 649 | pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; |
| 650 | } |
| 651 | |
| 652 | } |
| 653 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 654 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
Xavi Drudis Ferran | adb23a5 | 2011-02-28 00:10:37 +0000 | [diff] [blame] | 655 | static u8 mctGetProcessorPackageType(void) { |
| 656 | /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 657 | u32 BrandId = cpuid_ebx(0x80000001); |
| 658 | return (u8)((BrandId >> 28) & 0x0F); |
Xavi Drudis Ferran | adb23a5 | 2011-02-28 00:10:37 +0000 | [diff] [blame] | 659 | } |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 660 | #endif |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 661 | |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 662 | static void raminit_amdmct(struct sys_info *sysinfo) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 663 | { |
| 664 | struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); |
| 665 | struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; |
| 666 | |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 667 | printk(BIOS_DEBUG, "raminit_amdmct begin:\n"); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 668 | |
| 669 | mctAutoInitMCT_D(pMCTstat, pDCTstatA); |
| 670 | |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 671 | printk(BIOS_DEBUG, "raminit_amdmct end:\n"); |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 672 | } |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 673 | |
| 674 | static void amdmct_cbmem_store_info(struct sys_info *sysinfo) |
| 675 | { |
Timothy Pearson | 46b2271 | 2015-04-12 14:11:27 -0500 | [diff] [blame] | 676 | if (!sysinfo) |
| 677 | return; |
| 678 | |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 679 | /* Save memory info structures for use in ramstage */ |
| 680 | size_t i; |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 681 | struct DCTStatStruc *pDCTstatA = NULL; |
| 682 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 683 | if (!acpi_is_wakeup_s3()) { |
| 684 | /* Allocate memory */ |
| 685 | struct amdmct_memory_info *mem_info; |
| 686 | mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); |
| 687 | if (!mem_info) |
| 688 | return; |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 689 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 690 | printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 691 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 692 | /* Initialize memory */ |
| 693 | memset(mem_info, 0, sizeof(struct amdmct_memory_info)); |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 694 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 695 | /* Copy data */ |
| 696 | memcpy(&mem_info->mct_stat, &sysinfo->MCTstat, sizeof(struct MCTStatStruc)); |
| 697 | for (i = 0; i < MAX_NODES_SUPPORTED; i++) { |
| 698 | pDCTstatA = sysinfo->DCTstatA + i; |
| 699 | memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); |
| 700 | } |
| 701 | mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); |
| 702 | mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); |
Timothy Pearson | 46b2271 | 2015-04-12 14:11:27 -0500 | [diff] [blame] | 703 | |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 704 | /* Zero out invalid/unused pointers */ |
Timothy Pearson | 46b2271 | 2015-04-12 14:11:27 -0500 | [diff] [blame] | 705 | #if IS_ENABLED(CONFIG_DIMM_DDR3) |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 706 | for (i = 0; i < MAX_NODES_SUPPORTED; i++) { |
| 707 | mem_info->dct_stat[i].C_MCTPtr = NULL; |
| 708 | mem_info->dct_stat[i].C_DCTPtr[0] = NULL; |
| 709 | mem_info->dct_stat[i].C_DCTPtr[1] = NULL; |
| 710 | } |
Timothy Pearson | 46b2271 | 2015-04-12 14:11:27 -0500 | [diff] [blame] | 711 | #endif |
Timothy Pearson | 4ea0cc0 | 2015-09-05 18:39:34 -0500 | [diff] [blame] | 712 | } |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 713 | } |