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Marc Jones8ae8c882007-12-19 01:32:08 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Marc Jones8ae8c882007-12-19 01:32:08 +00003 *
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Marc Jones8ae8c882007-12-19 01:32:08 +000014 */
15
16#ifndef RAMINIT_H
17#define RAMINIT_H
18
19#if 0
Elyes HAOUAS04f8fd92016-09-19 10:24:34 -060020#if CONFIG_DIMM_SUPPORT == 0x0110
Marc Jones8ae8c882007-12-19 01:32:08 +000021//FBDIMM REG
22/* each channel can have 8 fbdimm */
23#define DIMM_SOCKETS 8
24struct mem_controller {
25 u32 node_id;
Antonello Dettorif65ccb22016-09-03 10:45:33 +020026 pci_devfn_t f0, f1, f2, f3, f4, f5;
Marc Jones8ae8c882007-12-19 01:32:08 +000027 /* channelA, channelB belong to DCT0,
28 * channelC, channelD belong to DCT1
29 * Each DCT may support one ganged logical FBDIMM ---> 128 bit
30 * or a single unganged channel --->64 bit
31 * a DCT can not support 2 unganged channels
32 * two DCTs can not be ganged
33 */
34 u8 spd_switch_addr;
35 u8 spd_addr[DIMM_SOCKETS*4];
36};
37
38#endif
39#endif
40
Elyes HAOUAS04f8fd92016-09-19 10:24:34 -060041//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004
Marc Jones8ae8c882007-12-19 01:32:08 +000042//DDR2 REG and unbuffered : Socket F 1027 and AM3
43/* every channel have 4 DDR2 DIMM for socket F
44 * 2 for socket M2/M3
45 * 1 for socket s1g1
46 */
47#define DIMM_SOCKETS 4
48struct mem_controller {
49 u32 node_id;
Antonello Dettorif65ccb22016-09-03 10:45:33 +020050 pci_devfn_t f0, f1, f2, f3, f4, f5;
Marc Jones8ae8c882007-12-19 01:32:08 +000051 /* channel0 is DCT0 --- channelA
52 * channel1 is DCT1 --- channelB
53 * can be ganged, a single dual-channel DCT ---> 128 bit
54 * or unganged a two single-channel DCTs ---> 64bit
55 * When the DCTs are ganged, the writes to DCT1 set of registers
56 * (F2x1XX) are ignored and reads return all 0's
57 * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
58 * and all the associated indexed registers, are still
59 * independently accessiable
60 */
61 /* FIXME: I will only support ganged mode for easy support */
62 u8 spd_switch_addr;
63 u8 spd_addr[DIMM_SOCKETS*2];
64};
65
66//#endif
67
68
69#endif