Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <arch/io.h> |
| 15 | #include <arch/cpu.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 16 | #include <arch/symbols.h> |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame^] | 17 | #include <bootmode.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 18 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 19 | #include <cbmem.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <fsp/api.h> |
| 22 | #include <fsp/util.h> |
| 23 | #include <memrange.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 24 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 25 | #include <reset.h> |
| 26 | #include <romstage_handoff.h> |
| 27 | #include <soc/intel/common/mrc_cache.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 28 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 29 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 30 | #include <timestamp.h> |
| 31 | |
| 32 | typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) |
| 33 | (void *raminit_upd, void **hob_list); |
| 34 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 35 | static void save_memory_training_data(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 36 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 37 | size_t mrc_data_size; |
| 38 | const void *mrc_data; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 39 | |
| 40 | if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) || s3wake) |
| 41 | return; |
| 42 | |
| 43 | mrc_data = fsp_find_nv_storage_data(&mrc_data_size); |
| 44 | if (!mrc_data) { |
| 45 | printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); |
| 46 | return; |
| 47 | } |
| 48 | |
| 49 | /* |
| 50 | * Save MRC Data to CBMEM. By always saving the data this forces |
| 51 | * a retrain after a trip through Chrome OS recovery path. The |
| 52 | * code which saves the data to flash doesn't write if the latest |
| 53 | * training data matches this one. |
| 54 | */ |
| 55 | if (mrc_cache_stash_data_with_version(mrc_data, mrc_data_size, |
| 56 | fsp_version) < 0) |
| 57 | printk(BIOS_ERR, "Failed to stash MRC data\n"); |
| 58 | } |
| 59 | |
| 60 | static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, |
| 61 | uint32_t fsp_version) |
| 62 | { |
| 63 | struct range_entry fsp_mem; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 64 | struct romstage_handoff *handoff; |
| 65 | |
| 66 | fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); |
| 67 | |
| 68 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 69 | if (!s3wake) { |
| 70 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 71 | range_entry_size(&fsp_mem)); |
| 72 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 73 | range_entry_size(&fsp_mem))) { |
| 74 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { |
| 75 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 76 | /* Failed S3 resume, reset to come up cleanly */ |
| 77 | hard_reset(); |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | /* make sure FSP memory is reserved in cbmem */ |
| 82 | if (range_entry_base(&fsp_mem) != |
| 83 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
| 84 | die("Failed to accommodate FSP reserved memory request"); |
| 85 | |
| 86 | /* Now that CBMEM is up, save the list so ramstage can use it */ |
| 87 | fsp_save_hob_list(hob_list_ptr); |
| 88 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 89 | save_memory_training_data(s3wake, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 90 | |
| 91 | /* Create romstage handof information */ |
| 92 | handoff = romstage_handoff_find_or_add(); |
| 93 | if (handoff != NULL) |
| 94 | handoff->s3_resume = s3wake; |
| 95 | else |
| 96 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 97 | |
| 98 | return FSP_SUCCESS; |
| 99 | } |
| 100 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 101 | static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, |
| 102 | uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 103 | { |
| 104 | const struct mrc_saved_data *mrc_cache; |
| 105 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 106 | arch_upd->NvsBufferPtr = NULL; |
| 107 | |
| 108 | if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) |
| 109 | return; |
| 110 | |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame^] | 111 | /* Don't use saved training data when recovery mode is enabled. */ |
| 112 | if (recovery_mode_enabled()) { |
| 113 | printk(BIOS_DEBUG, "Recovery mode. Not using MRC cache.\n"); |
| 114 | return; |
| 115 | } |
| 116 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 117 | if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { |
| 118 | printk(BIOS_DEBUG, "MRC cache was not found\n"); |
| 119 | return; |
| 120 | } |
| 121 | |
| 122 | /* MRC cache found */ |
| 123 | arch_upd->NvsBufferPtr = (void *)mrc_cache->data; |
| 124 | arch_upd->BootMode = s3wake ? |
| 125 | FSP_BOOT_ON_S3_RESUME: |
| 126 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 127 | printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", |
| 128 | mrc_cache->size, arch_upd->BootMode); |
| 129 | } |
| 130 | |
| 131 | static void fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, |
| 132 | bool s3wake, uint32_t fsp_version) |
| 133 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 134 | /* |
| 135 | * FSPM_UPD passed here is populated with default values provided by |
| 136 | * the blob itself. We let FSPM use top of CAR region of the size it |
| 137 | * requests. |
| 138 | * TODO: add checks to avoid overlap/conflict of CAR usage. |
| 139 | */ |
| 140 | arch_upd->StackBase = _car_region_end - arch_upd->StackSize; |
| 141 | |
| 142 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 143 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 144 | fsp_fill_mrc_cache(arch_upd, s3wake, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 148 | { |
| 149 | enum fsp_status status; |
| 150 | fsp_memory_init_fn fsp_raminit; |
| 151 | struct FSPM_UPD fspm_upd, *upd; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 152 | void *hob_list_ptr; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 153 | |
| 154 | post_code(0x34); |
| 155 | |
| 156 | upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); |
| 157 | |
| 158 | if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { |
| 159 | printk(BIOS_ERR, "Invalid FSPM signature\n"); |
| 160 | return FSP_INCOMPATIBLE_VERSION; |
| 161 | } |
| 162 | |
| 163 | /* Copy the default values from the UPD area */ |
| 164 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 165 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 166 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
| 167 | fspm_upd.FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); |
| 168 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 169 | /* Fill common settings on behalf of chipset. */ |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 170 | fsp_fill_common_arch_params(&fspm_upd.FspmArchUpd, s3wake, |
| 171 | hdr->fsp_revision); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 172 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 173 | /* Give SoC and mainboard a chance to update the UPD */ |
| 174 | platform_fsp_memory_init_params_cb(&fspm_upd); |
| 175 | |
| 176 | /* Call FspMemoryInit */ |
| 177 | fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); |
| 178 | printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); |
| 179 | printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 180 | printk(BIOS_SPEW, "\t%p: hob_list ptr\n", &hob_list_ptr); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 181 | |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 182 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 183 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 184 | status = fsp_raminit(&fspm_upd, &hob_list_ptr); |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 185 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 186 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 187 | |
| 188 | printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); |
| 189 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 190 | /* TODO: Is this the only thing that can happen? */ |
| 191 | if (status != FSP_SUCCESS) |
| 192 | return status; |
| 193 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 194 | return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 195 | } |
| 196 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 197 | /* Load the binary into the memory specified by the info header. */ |
| 198 | static enum cb_err load_fspm_mem(struct fsp_header *hdr, |
| 199 | const struct region_device *rdev) |
| 200 | { |
| 201 | struct memranges ranges; |
| 202 | struct range_entry freeranges[2]; |
| 203 | const struct range_entry *r; |
| 204 | uintptr_t fspm_begin; |
| 205 | uintptr_t fspm_end; |
| 206 | |
| 207 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 208 | return CB_ERR; |
| 209 | |
| 210 | fspm_begin = hdr->image_base; |
| 211 | fspm_end = fspm_begin + hdr->image_size; |
| 212 | |
| 213 | /* Build up memory map of romstage address space including CAR. */ |
| 214 | memranges_init_empty(&ranges, &freeranges[0], ARRAY_SIZE(freeranges)); |
| 215 | memranges_insert(&ranges, (uintptr_t)_car_region_start, |
| 216 | _car_relocatable_data_end - _car_region_start, 0); |
| 217 | memranges_insert(&ranges, (uintptr_t)_program, _program_size, 0); |
| 218 | memranges_each_entry(r, &ranges) { |
| 219 | if (fspm_end <= range_entry_base(r)) |
| 220 | continue; |
| 221 | if (fspm_begin >= range_entry_end(r)) |
| 222 | continue; |
| 223 | printk(BIOS_ERR, "FSPM overlaps currently running program.\n"); |
| 224 | return CB_ERR; |
| 225 | } |
| 226 | |
| 227 | /* Load binary into memory at provided address. */ |
| 228 | if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) |
| 229 | return CB_ERR; |
| 230 | |
| 231 | return CB_SUCCESS; |
| 232 | } |
| 233 | |
| 234 | /* Handle the case when FSPM is running XIP. */ |
| 235 | static enum cb_err load_fspm_xip(struct fsp_header *hdr, |
| 236 | const struct region_device *rdev) |
| 237 | { |
| 238 | void *base; |
| 239 | |
| 240 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 241 | return CB_ERR; |
| 242 | |
| 243 | base = rdev_mmap_full(rdev); |
| 244 | if ((uintptr_t)base != hdr->image_base) { |
| 245 | printk(BIOS_ERR, "FSPM XIP base does not match: %p vs %p\n", |
| 246 | (void *)(uintptr_t)hdr->image_base, base); |
| 247 | return CB_ERR; |
| 248 | } |
| 249 | |
| 250 | /* |
| 251 | * Since the component is XIP it's already in the address space. Thus, |
| 252 | * there's no need to rdev_munmap(). |
| 253 | */ |
| 254 | return CB_SUCCESS; |
| 255 | } |
| 256 | |
| 257 | enum fsp_status fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 258 | { |
| 259 | struct fsp_header hdr; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 260 | enum cb_err status; |
| 261 | struct cbfsf file_desc; |
| 262 | struct region_device file_data; |
| 263 | const char *name = CONFIG_FSP_M_CBFS; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 264 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 265 | if (cbfs_boot_locate(&file_desc, name, NULL)) { |
| 266 | printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 267 | return FSP_NOT_FOUND; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | cbfs_file_data(&file_data, &file_desc); |
| 271 | |
| 272 | if (IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES)) |
| 273 | status = load_fspm_mem(&hdr, &file_data); |
| 274 | else |
| 275 | status = load_fspm_xip(&hdr, &file_data); |
| 276 | |
| 277 | if (status != CB_SUCCESS) { |
| 278 | printk(BIOS_ERR, "Loading FSPM failed.\n"); |
| 279 | return FSP_NOT_FOUND; |
| 280 | } |
| 281 | |
| 282 | /* Signal that FSP component has been loaded. */ |
| 283 | prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 284 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 285 | return do_fsp_memory_init(&hdr, s3wake); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 286 | } |