Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <commonlib/helpers.h> |
| 18 | #include <cpu/x86/cache.h> |
| 19 | #include <cpu/x86/cr.h> |
| 20 | #include <cpu/x86/mtrr.h> |
| 21 | #include <cpu/x86/post_code.h> |
| 22 | #include <rules.h> |
| 23 | #include <intelblocks/msr.h> |
| 24 | |
| 25 | .global bootblock_pre_c_entry |
| 26 | bootblock_pre_c_entry: |
| 27 | |
| 28 | post_code(0x20) |
| 29 | |
| 30 | /* |
| 31 | * Use the MTRR default type MSR as a proxy for detecting INIT#. |
| 32 | * Reset the system if any known bits are set in that MSR. That is |
| 33 | * an indication of the CPU not being properly reset. |
| 34 | */ |
| 35 | check_for_clean_reset: |
| 36 | mov $MTRR_DEF_TYPE_MSR, %ecx |
| 37 | rdmsr |
| 38 | and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax |
| 39 | cmp $0, %eax |
| 40 | jz no_reset |
| 41 | /* perform warm reset */ |
| 42 | movw $0xcf9, %dx |
| 43 | movb $0x06, %al |
| 44 | outb %al, %dx |
| 45 | |
| 46 | no_reset: |
| 47 | post_code(0x21) |
| 48 | |
| 49 | /* Clear/disable fixed MTRRs */ |
| 50 | mov $fixed_mtrr_list_size, %ebx |
| 51 | xor %eax, %eax |
| 52 | xor %edx, %edx |
| 53 | |
| 54 | clear_fixed_mtrr: |
| 55 | add $-2, %ebx |
| 56 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 57 | wrmsr |
| 58 | jnz clear_fixed_mtrr |
| 59 | |
| 60 | post_code(0x22) |
| 61 | |
| 62 | /* Figure put how many MTRRs we have, and clear them out */ |
| 63 | mov $MTRR_CAP_MSR, %ecx |
| 64 | rdmsr |
| 65 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 66 | mov $MTRR_PHYS_BASE(0), %ecx |
| 67 | xor %eax, %eax |
| 68 | xor %edx, %edx |
| 69 | |
| 70 | clear_var_mtrr: |
| 71 | wrmsr |
| 72 | inc %ecx |
| 73 | wrmsr |
| 74 | inc %ecx |
| 75 | dec %ebx |
| 76 | jnz clear_var_mtrr |
| 77 | |
| 78 | post_code(0x23) |
| 79 | |
| 80 | /* Configure default memory type to uncacheable (UC) */ |
| 81 | mov $MTRR_DEF_TYPE_MSR, %ecx |
| 82 | rdmsr |
| 83 | /* Clear enable bits and set default type to UC. */ |
| 84 | and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ |
| 85 | MTRR_DEF_TYPE_FIX_EN), %eax |
| 86 | wrmsr |
| 87 | |
| 88 | /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB |
| 89 | * based on the physical address size supported for this processor |
| 90 | * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] |
| 91 | * |
| 92 | * Examples: |
| 93 | * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing |
| 94 | * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing |
| 95 | */ |
| 96 | |
| 97 | movl $0x80000008, %eax /* Address sizes leaf */ |
| 98 | cpuid |
| 99 | sub $32, %al |
| 100 | movzx %al, %eax |
| 101 | xorl %esi, %esi |
| 102 | bts %eax, %esi |
| 103 | dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ |
| 104 | |
| 105 | post_code(0x24) |
| 106 | |
| 107 | #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) |
| 108 | /* Configure CAR region as write-back (WB) */ |
| 109 | mov $MTRR_PHYS_BASE(0), %ecx |
| 110 | mov $CONFIG_DCACHE_RAM_BASE, %eax |
| 111 | or $MTRR_TYPE_WRBACK, %eax |
| 112 | xor %edx,%edx |
| 113 | wrmsr |
| 114 | |
| 115 | /* Configure the MTRR mask for the size region */ |
| 116 | mov $MTRR_PHYS_MASK(0), %ecx |
| 117 | mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ |
| 118 | dec %eax |
| 119 | not %eax |
| 120 | or $MTRR_PHYS_MASK_VALID, %eax |
| 121 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 122 | wrmsr |
| 123 | #elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ |
| 124 | /* Configure CAR region as write-back (WB) */ |
| 125 | mov $MTRR_PHYS_BASE(0), %ecx |
| 126 | mov $CONFIG_DCACHE_RAM_BASE, %eax |
| 127 | or $MTRR_TYPE_WRBACK, %eax |
| 128 | xor %edx,%edx |
| 129 | wrmsr |
| 130 | |
| 131 | mov $MTRR_PHYS_MASK(0), %ecx |
| 132 | mov $(512 * KiB), %eax /* size mask */ |
| 133 | dec %eax |
| 134 | not %eax |
| 135 | or $MTRR_PHYS_MASK_VALID, %eax |
| 136 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 137 | wrmsr |
| 138 | |
| 139 | mov $MTRR_PHYS_BASE(1), %ecx |
| 140 | mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax |
| 141 | or $MTRR_TYPE_WRBACK, %eax |
| 142 | xor %edx,%edx |
| 143 | wrmsr |
| 144 | |
| 145 | mov $MTRR_PHYS_MASK(1), %ecx |
| 146 | mov $(256 * KiB), %eax /* size mask */ |
| 147 | dec %eax |
| 148 | not %eax |
| 149 | or $MTRR_PHYS_MASK_VALID, %eax |
| 150 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 151 | wrmsr |
| 152 | #else |
| 153 | #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" |
| 154 | #endif |
| 155 | post_code(0x25) |
| 156 | |
| 157 | /* Enable variable MTRRs */ |
| 158 | mov $MTRR_DEF_TYPE_MSR, %ecx |
| 159 | rdmsr |
| 160 | or $MTRR_DEF_TYPE_EN, %eax |
| 161 | wrmsr |
| 162 | |
| 163 | /* Enable caching */ |
| 164 | mov %cr0, %eax |
| 165 | and $~(CR0_CD | CR0_NW), %eax |
| 166 | invd |
| 167 | mov %eax, %cr0 |
| 168 | |
| 169 | #if IS_ENABLED(CONFIG_INTEL_CAR_NEM) |
| 170 | jmp car_nem |
| 171 | #elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) |
| 172 | jmp car_cqos |
| 173 | #elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) |
| 174 | jmp car_nem_enhanced |
| 175 | #else |
| 176 | jmp .halt_forever /* In case nothing has selected */ |
| 177 | #endif |
| 178 | |
| 179 | .global car_init_done |
| 180 | car_init_done: |
| 181 | |
| 182 | post_code(0x29) |
| 183 | |
| 184 | /* Setup bootblock stack */ |
| 185 | mov $_car_stack_end, %esp |
| 186 | |
| 187 | /*push TSC value to stack*/ |
| 188 | movd %mm2, %eax |
| 189 | pushl %eax /* tsc[63:32] */ |
| 190 | movd %mm1, %eax |
| 191 | pushl %eax /* tsc[31:0] */ |
| 192 | |
| 193 | before_carstage: |
| 194 | post_code(0x2A) |
| 195 | |
| 196 | call bootblock_c_entry |
| 197 | /* Never reached */ |
| 198 | |
| 199 | .halt_forever: |
| 200 | post_code(POST_DEAD_CODE) |
| 201 | hlt |
| 202 | jmp .halt_forever |
| 203 | |
| 204 | fixed_mtrr_list: |
| 205 | .word MTRR_FIX_64K_00000 |
| 206 | .word MTRR_FIX_16K_80000 |
| 207 | .word MTRR_FIX_16K_A0000 |
| 208 | .word MTRR_FIX_4K_C0000 |
| 209 | .word MTRR_FIX_4K_C8000 |
| 210 | .word MTRR_FIX_4K_D0000 |
| 211 | .word MTRR_FIX_4K_D8000 |
| 212 | .word MTRR_FIX_4K_E0000 |
| 213 | .word MTRR_FIX_4K_E8000 |
| 214 | .word MTRR_FIX_4K_F0000 |
| 215 | .word MTRR_FIX_4K_F8000 |
| 216 | fixed_mtrr_list_size = . - fixed_mtrr_list |
| 217 | |
| 218 | #if IS_ENABLED(CONFIG_INTEL_CAR_NEM) |
| 219 | .global car_nem |
| 220 | car_nem: |
| 221 | /* Disable cache eviction (setup stage) */ |
| 222 | mov $MSR_EVICT_CTL, %ecx |
| 223 | rdmsr |
| 224 | or $0x1, %eax |
| 225 | wrmsr |
| 226 | |
| 227 | post_code(0x26) |
| 228 | |
| 229 | /* Clear the cache memory region. This will also fill up the cache */ |
| 230 | movl $CONFIG_DCACHE_RAM_BASE, %edi |
| 231 | movl $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 232 | shr $0x02, %ecx |
| 233 | xor %eax, %eax |
| 234 | cld |
| 235 | rep stosl |
| 236 | |
| 237 | post_code(0x27) |
| 238 | |
| 239 | /* Disable cache eviction (run stage) */ |
| 240 | mov $MSR_EVICT_CTL, %ecx |
| 241 | rdmsr |
| 242 | or $0x2, %eax |
| 243 | wrmsr |
| 244 | |
| 245 | post_code(0x28) |
| 246 | |
| 247 | jmp car_init_done |
| 248 | |
| 249 | #elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) |
| 250 | .global car_cqos |
| 251 | car_cqos: |
| 252 | /* |
| 253 | * Disable both L1 and L2 prefetcher. For yet-to-understood reason, |
| 254 | * prefetchers slow down filling cache with rep stos in CQOS mode. |
| 255 | */ |
| 256 | mov $MSR_PREFETCH_CTL, %ecx |
| 257 | rdmsr |
| 258 | or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax |
| 259 | wrmsr |
| 260 | |
| 261 | #if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE) |
| 262 | /* |
| 263 | * If CAR size is set to full L2 size, mask is calculated as all-zeros. |
| 264 | * This is not supported by the CPU/uCode. |
| 265 | */ |
| 266 | #error "CQOS CAR may not use whole L2 cache area" |
| 267 | #endif |
| 268 | |
| 269 | /* Calculate how many bits to be used for CAR */ |
| 270 | xor %edx, %edx |
| 271 | mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ |
| 272 | mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ |
| 273 | div %ecx /* result is in eax */ |
| 274 | mov %eax, %ecx /* save to ecx */ |
| 275 | mov $1, %ebx |
| 276 | shl %cl, %ebx |
| 277 | sub $1, %ebx /* resulting mask is is in ebx */ |
| 278 | |
| 279 | /* Set this mask for initial cache fill */ |
| 280 | mov $MSR_L2_QOS_MASK(0), %ecx |
| 281 | rdmsr |
| 282 | mov %bl, %al |
| 283 | wrmsr |
| 284 | |
| 285 | /* Set CLOS selector to 0 */ |
| 286 | mov $MSR_IA32_PQR_ASSOC, %ecx |
| 287 | rdmsr |
| 288 | and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ |
| 289 | wrmsr |
| 290 | |
| 291 | /* We will need to block CAR region from evicts */ |
| 292 | mov $MSR_L2_QOS_MASK(1), %ecx |
| 293 | rdmsr |
| 294 | /* Invert bits that are to be used for cache */ |
| 295 | mov %bl, %al |
| 296 | xor $~0, %al /* invert 8 bits */ |
| 297 | wrmsr |
| 298 | |
| 299 | post_code(0x26) |
| 300 | |
| 301 | /* Clear the cache memory region. This will also fill up the cache */ |
| 302 | movl $CONFIG_DCACHE_RAM_BASE, %edi |
| 303 | movl $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 304 | shr $0x02, %ecx |
| 305 | xor %eax, %eax |
| 306 | cld |
| 307 | rep stosl |
| 308 | |
| 309 | post_code(0x27) |
| 310 | |
| 311 | /* Cache is populated. Use mask 1 that will block evicts */ |
| 312 | mov $MSR_IA32_PQR_ASSOC, %ecx |
| 313 | rdmsr |
| 314 | and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ |
| 315 | or $1, %edx /* select mask 1 */ |
| 316 | wrmsr |
| 317 | |
| 318 | /* Enable prefetchers */ |
| 319 | mov $MSR_PREFETCH_CTL, %ecx |
| 320 | rdmsr |
| 321 | and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax |
| 322 | wrmsr |
| 323 | |
| 324 | post_code(0x28) |
| 325 | |
| 326 | jmp car_init_done |
| 327 | |
| 328 | #elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) |
| 329 | .global car_nem_enhanced |
| 330 | car_nem_enhanced: |
| 331 | /* Disable cache eviction (setup stage) */ |
| 332 | mov $MSR_EVICT_CTL, %ecx |
| 333 | rdmsr |
| 334 | or $0x1, %eax |
| 335 | wrmsr |
| 336 | post_code(0x26) |
| 337 | |
| 338 | /* Create n-way set associativity of cache */ |
| 339 | xorl %edi, %edi |
| 340 | find_llc_subleaf: |
| 341 | movl %edi, %ecx |
| 342 | movl $0x04, %eax |
| 343 | cpuid |
| 344 | inc %edi |
| 345 | and $0xe0, %al /* EAX[7:5] = Cache Level */ |
| 346 | cmp $0x60, %al /* Check to see if it is LLC */ |
| 347 | jnz find_llc_subleaf |
| 348 | |
| 349 | /* |
| 350 | * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE |
| 351 | * for 4/8/16 way of LLC |
| 352 | */ |
| 353 | shr $22, %ebx |
| 354 | inc %ebx |
| 355 | /* Calculate n-way associativity of LLC */ |
| 356 | mov %bl, %cl |
| 357 | |
| 358 | /* |
| 359 | * Maximizing RO cacheability while locking in the CAR to a |
| 360 | * single way since that particular way won't be victim candidate |
| 361 | * for evictions. |
| 362 | * This has been done after programing LLC_WAY_MASK_1 MSR |
| 363 | * with desired LLC way as mentioned below. |
| 364 | * |
| 365 | * Hence create Code and Data Size as per request |
| 366 | * Code Size (RO) : Up to 16M |
| 367 | * Data Size (RW) : Up to 256K |
| 368 | */ |
| 369 | movl $0x01, %eax |
| 370 | /* |
| 371 | * LLC Ways -> LLC_WAY_MASK_1: |
| 372 | * 4: 0x000E |
| 373 | * 8: 0x00FE |
| 374 | * 12: 0x0FFE |
| 375 | * 16: 0xFFFE |
| 376 | * |
| 377 | * These MSRs contain one bit per each way of LLC |
| 378 | * - If this bit is '0' - the way is protected from eviction |
| 379 | * - If this bit is '1' - the way is not protected from eviction |
| 380 | */ |
| 381 | shl %cl, %eax |
| 382 | subl $0x02, %eax |
| 383 | movl $MSR_IA32_L3_MASK_1, %ecx |
| 384 | xorl %edx, %edx |
| 385 | wrmsr |
| 386 | /* |
| 387 | * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 |
| 388 | * |
| 389 | * For SKL SOC, data size remains 256K consistently. |
| 390 | * Hence, creating 1-way associative cache for Data |
| 391 | */ |
| 392 | mov $MSR_IA32_L3_MASK_2, %ecx |
| 393 | mov $0x01, %eax |
| 394 | xorl %edx, %edx |
| 395 | wrmsr |
| 396 | /* |
| 397 | * Set MSR_IA32_PQR_ASSOC = 0x02 |
| 398 | * |
| 399 | * Possible values: |
| 400 | * 0: Default value, no way mask should be applied |
| 401 | * 1: Apply way mask 1 to LLC |
| 402 | * 2: Apply way mask 2 to LLC |
| 403 | * 3: Shouldn't be use in NEM Mode |
| 404 | */ |
| 405 | movl $MSR_IA32_PQR_ASSOC, %ecx |
| 406 | movl $0x02, %eax |
| 407 | xorl %edx, %edx |
| 408 | wrmsr |
| 409 | |
| 410 | movl $CONFIG_DCACHE_RAM_BASE, %edi |
| 411 | movl $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 412 | shr $0x02, %ecx |
| 413 | xor %eax, %eax |
| 414 | cld |
| 415 | rep stosl |
| 416 | /* |
| 417 | * Set MSR_IA32_PQR_ASSOC = 0x01 |
| 418 | * At this stage we apply LLC_WAY_MASK_1 to the cache. |
| 419 | * i.e. way 0 is protected from eviction. |
| 420 | */ |
| 421 | movl $MSR_IA32_PQR_ASSOC, %ecx |
| 422 | movl $0x01, %eax |
| 423 | xorl %edx, %edx |
| 424 | wrmsr |
| 425 | |
| 426 | post_code(0x27) |
| 427 | /* |
| 428 | * Enable No-Eviction Mode Run State by setting |
| 429 | * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. |
| 430 | */ |
| 431 | |
| 432 | movl $MSR_EVICT_CTL, %ecx |
| 433 | rdmsr |
| 434 | orl $0x02, %eax |
| 435 | wrmsr |
| 436 | |
| 437 | post_code(0x28) |
| 438 | |
| 439 | jmp car_init_done |
| 440 | #endif |