blob: 94ee5b18ad94474b445e90484bd336dfeaaa9554 [file] [log] [blame]
David Hendricks6d5b2f72016-11-17 14:19:51 -08001{
2 /* 2 Micron DDMT52L256M64D2PP-107 chips */
3 {
4 {
5 .rank = 0x1,
6 .col = 0xA,
7 .bk = 0x3,
8 .bw = 0x2,
9 .dbw = 0x2,
10 .row_3_4 = 0x0,
11 .cs0_row = 0xF,
12 .cs1_row = 0xF
13 },
14 {
15 .rank = 0x1,
16 .col = 0xA,
17 .bk = 0x3,
18 .bw = 0x2,
19 .dbw = 0x2,
20 .row_3_4 = 0x0,
21 .cs0_row = 0xF,
22 .cs1_row = 0xF
23 }
24 },
25 {
26 .togcnt1u = 0x215,
27 .tinit = 0xC8,
28 .trsth = 0x0,
29 .togcnt100n = 0x35,
30 .trefi = 0x26,
31 .tmrd = 0x2,
32 .trfc = 0x70,
33 .trp = 0x2000D,
34 .trtw = 0x6,
35 .tal = 0x0,
36 .tcl = 0x8,
37 .tcwl = 0x4,
38 .tras = 0x17,
39 .trc = 0x24,
40 .trcd = 0xD,
41 .trrd = 0x6,
42 .trtp = 0x4,
43 .twr = 0x8,
44 .twtr = 0x4,
45 .texsr = 0x76,
46 .txp = 0x4,
47 .txpdll = 0x0,
48 .tzqcs = 0x30,
49 .tzqcsi = 0x0,
50 .tdqs = 0x1,
51 .tcksre = 0x2,
52 .tcksrx = 0x2,
53 .tcke = 0x4,
54 .tmod = 0x0,
55 .trstl = 0x0,
56 .tzqcl = 0xC0,
57 .tmrr = 0x4,
58 .tckesr = 0x8,
59 .tdpd = 0x1F4
60 },
61 {
62 .dtpr0 = 0x48D7DD93,
63 .dtpr1 = 0x187008D8,
64 .dtpr2 = 0x121076,
65 .mr[0] = 0x0,
66 .mr[1] = 0xC3,
67 .mr[2] = 0x6,
68 .mr[3] = 0x2
69 },
70 .noc_timing = 0x20D266A4,
71 .noc_activate = 0x5B6,
72 .ddrconfig = 3,
73 .ddr_freq = 533*MHz,
74 .dramtype = LPDDR3,
75 .num_channels = 2,
76 .stride = 9,
77 .odt = 1,
78},