blob: 20eee7f34b804d58e4b4a8051686d28a41f13c27 [file] [log] [blame]
Thejaswani Puttae3443d82019-07-18 16:23:20 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <ec/google/wilco/romstage.h>
17#include <soc/cnl_memcfg_init.h>
18#include <soc/romstage.h>
19
20static const struct cnl_mb_cfg memcfg = {
21 /* Access memory info through SMBUS. */
22 .spd[0] = {
23 .read_type = READ_SMBUS,
24 .spd_spec = {.spd_smbus_address = 0xa0},
25 },
26 .spd[1] = {.read_type = NOT_EXISTING},
27 .spd[2] = {
28 .read_type = READ_SMBUS,
29 .spd_spec = {.spd_smbus_address = 0xa4},
30 },
31 .spd[3] = {.read_type = NOT_EXISTING},
32
33 /*
34 * The dqs_map arrays map the ddr4 pins to the SoC pins
35 * for both channels.
36 *
37 * the index = pin number on ddr4 part
38 * the value = pin number on SoC
39 */
40 .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
41 .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
42
43 /* Baseboard uses 121, 81 and 100 rcomp resistors */
44 .rcomp_resistor = {121, 81, 100},
45
46 /*
47 * Baseboard Rcomp target values.
48 */
49 .rcomp_targets = {100, 40, 20, 20, 26},
50
51 /* Disable Early Command Training */
52 .ect = 0,
53
54 /* Base on board design */
55 .vref_ca_config = 2,
56};
57
58void mainboard_memory_init_params(FSPM_UPD *memupd)
59{
60 wilco_ec_romstage_init();
61
62 cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
63}