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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
21config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000022 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000023 help
24 Append an extra string to the end of the coreboot version.
25
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
30
Patrick Georgi4b8a2412010-02-09 19:35:16 +000031config CBFS_PREFIX
32 string "CBFS prefix to use"
33 default "fallback"
34 help
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
37
Vadim Bendeburyadcb0952014-05-01 12:23:09 -070038config COMMON_CBFS_SPI_WRAPPER
39 bool
40 default n
41 depends on SPI_FLASH
42 depends on !ARCH_X86
43 help
44 Use common wrapper to interface CBFS to SPI bootrom.
45
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080046config MULTIPLE_CBFS_INSTANCES
Martin Roth595e7772015-04-26 18:53:26 -060047 bool "Multiple CBFS instances in the bootrom"
48 default n
Martin Roth595e7772015-04-26 18:53:26 -060049 help
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080054
Patrick Georgi23d89cc2010-03-16 01:17:19 +000055choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020056 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000057 default COMPILER_GCC
58 help
59 This option allows you to select the compiler used for building
60 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070061 You must build the coreboot crosscompiler for the board that you
62 have selected.
63
64 To build all the GCC crosscompilers (takes a LONG time), run:
65 make crossgcc
66
67 For help on individual architectures, run the command:
68 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000069
70config COMPILER_GCC
71 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020072 help
73 Use the GNU Compiler Collection (GCC) to build coreboot.
74
75 For details see http://gcc.gnu.org.
76
Patrick Georgi23d89cc2010-03-16 01:17:19 +000077config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070078 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020079 help
Martin Rotha5a628e82016-01-19 12:01:09 -070080 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
82 make clang
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
85 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020086
87 For details see http://clang.llvm.org.
88
Patrick Georgi23d89cc2010-03-16 01:17:19 +000089endchoice
90
Patrick Georgi9b0de712013-12-29 18:45:23 +010091config ANY_TOOLCHAIN
92 bool "Allow building with any toolchain"
93 default n
94 depends on COMPILER_GCC
95 help
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
100
Patrick Georgi516a2a72010-03-25 21:45:25 +0000101config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200102 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000103 default n
104 help
105 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200106
107 Requires the ccache utility in your system $PATH.
108
109 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000110
Sol Boucher69b88bf2015-02-26 11:47:19 -0800111config FMD_GENPARSER
112 bool "Generate flashmap descriptor parser using flex and bison"
113 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800114 help
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
117
118 Otherwise, say N to use the provided pregenerated scanner/parser.
119
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000120config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
122 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000123 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200124 Enable this option if you are working on the sconfig device tree
Sol Boucher69b88bf2015-02-26 11:47:19 -0800125 parser and made changes to sconfig.l or sconfig.y.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200126
Sol Boucher69b88bf2015-02-26 11:47:19 -0800127 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000128
Joe Korty6d772522010-05-19 18:41:15 +0000129config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
131 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000132 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000133 help
134 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200135 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000136
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600137config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
139 default n
140 depends on USE_OPTION_TABLE
141 help
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
145
Julius Wernercdf92ea2014-12-09 12:18:00 -0800146config UNCOMPRESSED_RAMSTAGE
147 bool
148 default n
149
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000150config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
Julius Wernercdf92ea2014-12-09 12:18:00 -0800152 default y if !UNCOMPRESSED_RAMSTAGE
153 default n
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000154 help
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200157 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000158
Julius Werner09f29212015-09-29 13:51:35 -0700159config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
Martin Rothf2e04612016-03-09 15:50:23 -0700161 depends on !ARCH_X86
162 default y
Julius Werner09f29212015-09-29 13:51:35 -0700163 help
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
169
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200170config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200171 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200172 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200173 help
174 Include the .config file that was used to compile coreboot
175 in the (CBFS) ROM image. This is useful if you want to know which
176 options were used to build a specific coreboot.rom image.
177
Daniele Forsi53847a22014-07-22 18:00:56 +0200178 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200179
180 You can use the following command to easily list the options:
181
182 grep -a CONFIG_ coreboot.rom
183
184 Alternatively, you can also use cbfstool to print the image
185 contents (including the raw 'config' item we're looking for).
186
187 Example:
188
189 $ cbfstool coreboot.rom print
190 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
191 offset 0x0
192 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600193
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200194 Name Offset Type Size
195 cmos_layout.bin 0x0 cmos layout 1159
196 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200197 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200198 fallback/payload 0x80dc0 payload 51526
199 config 0x8d740 raw 3324
200 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200201
Furquan Shaikh94b18a12016-05-04 23:25:16 -0700202config NO_XIP_EARLY_STAGES
203 bool
204 default n if ARCH_X86
205 default y
206 help
207 Identify if --xip parameter needs to be passed into cbfstool for early
208 stages.
209
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300210config EARLY_CBMEM_INIT
Kyösti Mälkki3bf38542014-12-18 22:22:04 +0200211 def_bool !LATE_CBMEM_INIT
212
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700213config COLLECT_TIMESTAMPS
214 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300215 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700216 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200217 Make coreboot create a table of timer-ID/timer-value pairs to
218 allow measuring time spent at different phases of the boot process.
219
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200220config USE_BLOBS
221 bool "Allow use of binary-only repository"
222 default n
223 help
224 This draws in the blobs repository, which contains binary files that
225 might be required for some chipsets or boards.
226 This flag ensures that a "Free" option remains available for users.
227
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800228config COVERAGE
229 bool "Code coverage support"
230 depends on COMPILER_GCC
231 default n
232 help
233 Add code coverage support for coreboot. This will store code
234 coverage information in CBMEM for extraction from user space.
235 If unsure, say N.
236
Stefan Reinauer58470e32014-10-17 13:08:36 +0200237config RELOCATABLE_MODULES
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200238 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200239 default n
240 help
241 If RELOCATABLE_MODULES is selected then support is enabled for
242 building relocatable modules in the RAM stage. Those modules can be
243 loaded anywhere and all the relocations are handled automatically.
244
245config RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200246 depends on EARLY_CBMEM_INIT
Stefan Reinauer58470e32014-10-17 13:08:36 +0200247 bool "Build the ramstage to be relocatable in 32-bit address space."
248 default n
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200249 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200250 help
251 The reloctable ramstage support allows for the ramstage to be built
252 as a relocatable module. The stage loader can identify a place
253 out of the OS way so that copying memory is unnecessary during an S3
254 wake. When selecting this option the romstage is responsible for
255 determing a stack location to use for loading the ramstage.
256
257config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
258 depends on RELOCATABLE_RAMSTAGE
259 bool "Cache the relocated ramstage outside of cbmem."
260 default n
261 help
262 The relocated ramstage is saved in an area specified by the
263 by the board and/or chipset.
264
Furquan Shaikh1e162bf2016-05-06 09:20:35 -0700265config NO_STAGE_CACHE
266 bool
267 default n
268 help
269 Do not save any component in stage cache for resume path. On resume,
270 all components would be read back from CBFS again.
271
Aaron Durbin0424c952015-03-28 23:56:22 -0500272config FLASHMAP_OFFSET
273 hex "Flash Map Offset"
Vladimir Serbinenko144eea02016-02-10 02:36:04 +0100274 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
275 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
Aaron Durbin0424c952015-03-28 23:56:22 -0500276 default CBFS_SIZE if !ARCH_X86
277 default 0
278 help
279 Offset of flash map in firmware image
280
Julius Werner86fc11d2015-10-09 13:37:58 -0700281# TODO: This doesn't belong here, move to src/arch/x86/Kconfig
Stefan Reinauer58470e32014-10-17 13:08:36 +0200282choice
283 prompt "Bootblock behaviour"
284 default BOOTBLOCK_SIMPLE
285
286config BOOTBLOCK_SIMPLE
287 bool "Always load fallback"
288
289config BOOTBLOCK_NORMAL
290 bool "Switch to normal if CMOS says so"
291
292endchoice
293
Julius Werner86fc11d2015-10-09 13:37:58 -0700294# To be selected by arch, SoC or mainboard if it does not want use the normal
295# src/lib/bootblock.c#main() C entry point.
296config BOOTBLOCK_CUSTOM
297 bool
298 default n
299
Stefan Reinauer58470e32014-10-17 13:08:36 +0200300config BOOTBLOCK_SOURCE
301 string
302 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
303 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
304
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700305# To be selected by arch or platform if a C environment is available during the
306# bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
307config C_ENVIRONMENT_BOOTBLOCK
Martin Roth95f33f4e2016-01-21 12:30:52 -0700308 bool
309 default n
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700310
Timothy Pearson44724082015-03-16 11:47:45 -0500311config SKIP_MAX_REBOOT_CNT_CLEAR
312 bool "Do not clear reboot count after successful boot"
313 default n
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600314 depends on BOOTBLOCK_NORMAL
Timothy Pearson44724082015-03-16 11:47:45 -0500315 help
316 Do not clear the reboot count immediately after successful boot.
317 Set to allow the payload to control normal/fallback image recovery.
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600318 Note that it is the responsibility of the payload to reset the
319 normal boot bit to 1 after each successsful boot.
Timothy Pearson44724082015-03-16 11:47:45 -0500320
Stefan Reinauer58470e32014-10-17 13:08:36 +0200321config UPDATE_IMAGE
322 bool "Update existing coreboot.rom image"
323 default n
324 help
325 If this option is enabled, no new coreboot.rom file
326 is created. Instead it is expected that there already
327 is a suitable file for further processing.
328 The bootblock will not be modified.
329
Martin Roth5942e062016-01-20 14:59:21 -0700330 If unsure, select 'N'
331
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700332config GENERIC_GPIO_LIB
333 bool
334 default n
335 help
336 If enabled, compile the generic GPIO library. A "generic" GPIO
337 implies configurability usually found on SoCs, particularly the
338 ability to control internal pull resistors.
339
340config BOARD_ID_AUTO
341 bool
342 default n
343 help
344 Mainboards that can read a board ID from the hardware straps
345 (ie. GPIO) select this configuration option.
346
347config BOARD_ID_MANUAL
Vladimir Serbinenko1e161422015-05-30 22:47:22 +0200348 bool
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700349 default n
350 depends on !BOARD_ID_AUTO
351 help
352 If you want to maintain a board ID, but the hardware does not
353 have straps to automatically determine the ID, you can say Y
354 here and add a file named 'board_id' to CBFS. If you don't know
355 what this is about, say N.
356
357config BOARD_ID_STRING
358 string "Board ID"
359 default "(none)"
360 depends on BOARD_ID_MANUAL
361 help
362 This string is placed in the 'board_id' CBFS file for indicating
363 board type.
364
David Hendricks627b3bd2014-11-03 17:42:09 -0800365config RAM_CODE_SUPPORT
Vladimir Serbinenko8ef9c562015-05-30 22:55:44 +0200366 bool
David Hendricks627b3bd2014-11-03 17:42:09 -0800367 default n
368 help
369 If enabled, coreboot discovers RAM configuration (value obtained by
370 reading board straps) and stores it in coreboot table.
371
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400372config BOOTSPLASH_IMAGE
373 bool "Add a bootsplash image"
374 help
375 Select this option if you have a bootsplash image that you would
376 like to add to your ROM.
377
378 This will only add the image to the ROM. To actually run it check
379 options under 'Display' section.
380
381config BOOTSPLASH_FILE
382 string "Bootsplash path and filename"
383 depends on BOOTSPLASH_IMAGE
384 default "bootsplash.jpg"
385 help
386 The path and filename of the file to use as graphical bootsplash
387 screen. The file format has to be jpg.
388
Uwe Hermannc04be932009-10-05 13:55:28 +0000389endmenu
390
Alexander Couzens77103792015-04-16 02:03:26 +0200391source "src/acpi/Kconfig"
392
Martin Roth026e4dc2015-06-19 23:17:15 -0600393menu "Mainboard"
394
Stefan Reinauera48ca842015-04-04 01:58:28 +0200395source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000396
Martin Roth59ff3402016-02-09 09:06:46 -0700397# defaults for CBFS_SIZE are set at the end of the file.
Martin Roth026e4dc2015-06-19 23:17:15 -0600398config CBFS_SIZE
399 hex "Size of CBFS filesystem in ROM"
Martin Roth026e4dc2015-06-19 23:17:15 -0600400 help
401 This is the part of the ROM actually managed by CBFS, located at the
402 end of the ROM (passed through cbfstool -o) on x86 and at at the start
403 of the ROM (passed through cbfstool -s) everywhere else. It defaults
404 to span the whole ROM on all but Intel systems that use an Intel Firmware
405 Descriptor. It can be overridden to make coreboot live alongside other
406 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
407 binaries.
408
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200409config FMDFILE
410 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100411 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200412 default ""
413 help
414 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
415 but in some cases more complex setups are required.
416 When an fmd is specified, it overrides the default format.
417
Martin Rothda1ca202015-12-26 16:51:16 -0700418endmenu
419
Martin Rothb09a5692016-01-24 19:38:33 -0700420# load site-local kconfig to allow user specific defaults and overrides
421source "site-local/Kconfig"
422
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200423config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600424 default n
425 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200426
Werner Zehc0fb3612016-01-14 15:08:36 +0100427config CBFS_AUTOGEN_ATTRIBUTES
428 default n
429 bool
430 help
431 If this option is selected, every file in cbfs which has a constraint
432 regarding position or alignment will get an additional file attribute
433 which describes this constraint.
434
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000435menu "Chipset"
436
Duncan Lauried2119762015-06-08 18:11:56 -0700437comment "SoC"
438source "src/soc/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000439comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200440source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000441comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200442source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000443comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200444source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000445comment "Super I/O"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200446source "src/superio/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000447comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200448source "src/ec/acpi/Kconfig"
449source "src/ec/*/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800450# FIXME move to vendorcode
Marc Jones78687972015-04-22 23:16:31 -0600451source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000452
Martin Roth59aa2b12015-06-20 16:17:12 -0600453source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600454source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600455
Martin Rothe1523ec2015-06-19 22:30:43 -0600456source "src/arch/*/Kconfig"
457
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000458endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000459
Stefan Reinauera48ca842015-04-04 01:58:28 +0200460source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800461
Rudolf Marekd9c25492010-05-16 15:31:53 +0000462menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200463source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800464source "src/drivers/*/*/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000465endmenu
466
Patrick Georgi0770f252015-04-22 13:28:21 +0200467config RTC
468 bool
469 default n
470
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700471config TPM
472 bool
473 default n
474 select LPC_TPM if ARCH_X86
Gabe Black51edd542013-09-30 23:00:33 -0700475 select I2C_TPM if ARCH_ARM
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700476 select I2C_TPM if ARCH_ARM64
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700477 help
478 Enable this option to enable TPM support in coreboot.
479
480 If unsure, say N.
481
Kyösti Mälkkieaee6e22014-04-30 01:35:29 +0300482config RAMTOP
483 hex
484 default 0x200000
485 depends on ARCH_X86
486
Patrick Georgi0588d192009-08-12 15:00:51 +0000487config HEAP_SIZE
488 hex
Myles Watson04000f42009-10-16 19:12:49 +0000489 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000490
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700491config STACK_SIZE
492 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700493 default 0x1000 if ARCH_X86
494 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700495
Patrick Georgi0588d192009-08-12 15:00:51 +0000496config MAX_CPUS
497 int
498 default 1
499
500config MMCONF_SUPPORT_DEFAULT
501 bool
502 default n
503
504config MMCONF_SUPPORT
505 bool
506 default n
507
Kyösti Mälkki5687fc92013-11-28 18:11:49 +0200508config BOOTMODE_STRAPS
509 bool
510 default n
511
Stefan Reinauera48ca842015-04-04 01:58:28 +0200512source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000513
514config HAVE_ACPI_RESUME
515 bool
516 default n
517
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600518config RESUME_PATH_SAME_AS_BOOT
519 bool
520 default y if ARCH_X86
521 depends on HAVE_ACPI_RESUME
522 help
523 This option indicates that when a system resumes it takes the
524 same path as a regular boot. e.g. an x86 system runs from the
525 reset vector at 0xfffffff0 on both resume and warm/cold boot.
526
Patrick Georgi0588d192009-08-12 15:00:51 +0000527config HAVE_HARD_RESET
528 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000529 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000530 help
531 This variable specifies whether a given board has a hard_reset
532 function, no matter if it's provided by board code or chipset code.
533
Timothy Pearson44d53422015-05-18 16:04:10 -0500534config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
535 bool
536 default n
537
Timothy Pearson7b22d842015-08-28 19:52:05 -0500538config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
539 bool
540 default n
541 help
542 This should be enabled on certain plaforms, such as the AMD
543 SR565x, that cannot handle concurrent CBFS accesses from
544 multiple APs during early startup.
545
Timothy Pearsonc764c742015-08-28 20:48:17 -0500546config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
547 bool
548 default n
549
Aaron Durbina4217912013-04-29 22:31:51 -0500550config HAVE_MONOTONIC_TIMER
551 def_bool n
552 help
553 The board/chipset provides a monotonic timer.
554
Aaron Durbine5e36302014-09-25 10:05:15 -0500555config GENERIC_UDELAY
556 def_bool n
557 depends on HAVE_MONOTONIC_TIMER
558 help
559 The board/chipset uses a generic udelay function utilizing the
560 monotonic timer.
561
Aaron Durbin340ca912013-04-30 09:58:12 -0500562config TIMER_QUEUE
563 def_bool n
564 depends on HAVE_MONOTONIC_TIMER
565 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300566 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500567
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500568config COOP_MULTITASKING
569 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500570 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500571 help
572 Cooperative multitasking allows callbacks to be multiplexed on the
573 main thread of ramstage. With this enabled it allows for multiple
574 execution paths to take place when they have udelay() calls within
575 their code.
576
577config NUM_THREADS
578 int
579 default 4
580 depends on COOP_MULTITASKING
581 help
582 How many execution threads to cooperatively multitask with.
583
Patrick Georgi0588d192009-08-12 15:00:51 +0000584config HAVE_OPTION_TABLE
585 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000586 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000587 help
588 This variable specifies whether a given board has a cmos.layout
589 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000590 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000591
Patrick Georgi0588d192009-08-12 15:00:51 +0000592config PIRQ_ROUTE
593 bool
594 default n
595
596config HAVE_SMI_HANDLER
597 bool
598 default n
599
600config PCI_IO_CFG_EXT
601 bool
602 default n
603
604config IOAPIC
605 bool
606 default n
607
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200608config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700609 hex
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200610 default 0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700611
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000612# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000613config VIDEO_MB
614 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000615 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000616
Myles Watson45bb25f2009-09-22 18:49:08 +0000617config USE_WATCHDOG_ON_BOOT
618 bool
619 default n
620
621config VGA
622 bool
623 default n
624 help
625 Build board-specific VGA code.
626
627config GFXUMA
628 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000629 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000630 help
631 Enable Unified Memory Architecture for graphics.
632
Myles Watsonb8e20272009-10-15 13:35:47 +0000633config HAVE_ACPI_TABLES
634 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000635 help
636 This variable specifies whether a given board has ACPI table support.
637 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000638
639config HAVE_MP_TABLE
640 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000641 help
642 This variable specifies whether a given board has MP table support.
643 It is usually set in mainboard/*/Kconfig.
644 Whether or not the MP table is actually generated by coreboot
645 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000646
647config HAVE_PIRQ_TABLE
648 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000649 help
650 This variable specifies whether a given board has PIRQ table support.
651 It is usually set in mainboard/*/Kconfig.
652 Whether or not the PIRQ table is actually generated by coreboot
653 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000654
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500655config MAX_PIRQ_LINKS
656 int
657 default 4
658 help
659 This variable specifies the number of PIRQ interrupt links which are
660 routable. On most chipsets, this is 4, INTA through INTD. Some
661 chipsets offer more than four links, commonly up to INTH. They may
662 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
663 table specifies links greater than 4, pirq_route_irqs will not
664 function properly, unless this variable is correctly set.
665
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200666config COMMON_FADT
667 bool
668 default n
669
Aaron Durbin9420a522015-11-17 16:31:00 -0600670config ACPI_NHLT
671 bool
672 default n
673 help
674 Build support for NHLT (non HD Audio) ACPI table generation.
675
Myles Watsond73c1b52009-10-26 15:14:07 +0000676#These Options are here to avoid "undefined" warnings.
677#The actual selection and help texts are in the following menu.
678
Uwe Hermann168b11b2009-10-07 16:15:40 +0000679menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000680
Myles Watsonb8e20272009-10-15 13:35:47 +0000681config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800682 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
683 bool
684 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000685 help
686 Generate an MP table (conforming to the Intel MultiProcessor
687 specification 1.4) for this board.
688
689 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000690
Myles Watsonb8e20272009-10-15 13:35:47 +0000691config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800692 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
693 bool
694 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000695 help
696 Generate a PIRQ table for this board.
697
698 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000699
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200700config GENERATE_SMBIOS_TABLES
701 depends on ARCH_X86
702 bool "Generate SMBIOS tables"
703 default y
704 help
705 Generate SMBIOS tables for this board.
706
707 If unsure, say Y.
708
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200709config SMBIOS_PROVIDED_BY_MOBO
710 bool
711 default n
712
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200713config MAINBOARD_SERIAL_NUMBER
714 string "SMBIOS Serial Number"
715 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200716 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200717 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600718 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200719 The Serial Number to store in SMBIOS structures.
720
721config MAINBOARD_VERSION
722 string "SMBIOS Version Number"
723 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200724 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200725 default "1.0"
726 help
727 The Version Number to store in SMBIOS structures.
728
729config MAINBOARD_SMBIOS_MANUFACTURER
730 string "SMBIOS Manufacturer"
731 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200732 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200733 default MAINBOARD_VENDOR
734 help
735 Override the default Manufacturer stored in SMBIOS structures.
736
737config MAINBOARD_SMBIOS_PRODUCT_NAME
738 string "SMBIOS Product name"
739 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200740 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200741 default MAINBOARD_PART_NUMBER
742 help
743 Override the default Product name stored in SMBIOS structures.
744
Myles Watson45bb25f2009-09-22 18:49:08 +0000745endmenu
746
Martin Roth21c06502016-02-04 19:52:27 -0700747source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000748
Uwe Hermann168b11b2009-10-07 16:15:40 +0000749menu "Debugging"
750
751# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000752config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000753 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200754 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100755 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000756 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000757 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000758 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000759
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200760config GDB_WAIT
761 bool "Wait for a GDB connection"
762 default n
763 depends on GDB_STUB
764 help
765 If enabled, coreboot will wait for a GDB connection.
766
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800767config FATAL_ASSERTS
768 bool "Halt when hitting a BUG() or assertion error"
769 default n
770 help
771 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
772
Stefan Reinauerfe422182012-05-02 16:33:18 -0700773config DEBUG_CBFS
774 bool "Output verbose CBFS debug messages"
775 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700776 help
777 This option enables additional CBFS related debug messages.
778
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000779config HAVE_DEBUG_RAM_SETUP
780 def_bool n
781
Uwe Hermann01ce6012010-03-05 10:03:50 +0000782config DEBUG_RAM_SETUP
783 bool "Output verbose RAM init debug messages"
784 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000785 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000786 help
787 This option enables additional RAM init related debug messages.
788 It is recommended to enable this when debugging issues on your
789 board which might be RAM init related.
790
791 Note: This option will increase the size of the coreboot image.
792
793 If unsure, say N.
794
Patrick Georgie82618d2010-10-01 14:50:12 +0000795config HAVE_DEBUG_CAR
796 def_bool n
797
Peter Stuge5015f792010-11-10 02:00:32 +0000798config DEBUG_CAR
799 def_bool n
800 depends on HAVE_DEBUG_CAR
801
802if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000803# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
804# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000805config DEBUG_CAR
806 bool "Output verbose Cache-as-RAM debug messages"
807 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000808 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000809 help
810 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000811endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000812
Myles Watson80e914ff2010-06-01 19:25:31 +0000813config DEBUG_PIRQ
814 bool "Check PIRQ table consistency"
815 default n
816 depends on GENERATE_PIRQ_TABLE
817 help
818 If unsure, say N.
819
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000820config HAVE_DEBUG_SMBUS
821 def_bool n
822
Uwe Hermann01ce6012010-03-05 10:03:50 +0000823config DEBUG_SMBUS
824 bool "Output verbose SMBus debug messages"
825 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000826 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000827 help
828 This option enables additional SMBus (and SPD) debug messages.
829
830 Note: This option will increase the size of the coreboot image.
831
832 If unsure, say N.
833
834config DEBUG_SMI
835 bool "Output verbose SMI debug messages"
836 default n
837 depends on HAVE_SMI_HANDLER
Martin Roth3a543182015-09-28 15:27:24 -0600838 select SPI_FLASH_SMM if SPI_CONSOLE
Uwe Hermann01ce6012010-03-05 10:03:50 +0000839 help
840 This option enables additional SMI related debug messages.
841
842 Note: This option will increase the size of the coreboot image.
843
844 If unsure, say N.
845
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000846config DEBUG_SMM_RELOCATION
847 bool "Debug SMM relocation code"
848 default n
849 depends on HAVE_SMI_HANDLER
850 help
851 This option enables additional SMM handler relocation related
852 debug messages.
853
854 Note: This option will increase the size of the coreboot image.
855
856 If unsure, say N.
857
Uwe Hermanna953f372010-11-10 00:14:32 +0000858# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
859# printk(BIOS_DEBUG, ...) calls.
860config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800861 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
862 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000863 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000864 help
865 This option enables additional malloc related debug messages.
866
867 Note: This option will increase the size of the coreboot image.
868
869 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300870
871# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
872# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300873config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800874 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
875 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300876 default n
877 help
878 This option enables additional ACPI related debug messages.
879
880 Note: This option will slightly increase the size of the coreboot image.
881
882 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300883
Uwe Hermanna953f372010-11-10 00:14:32 +0000884# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
885# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000886config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800887 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
888 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000889 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000890 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000891 help
892 This option enables additional x86emu related debug messages.
893
894 Note: This option will increase the time to emulate a ROM.
895
896 If unsure, say N.
897
Uwe Hermann01ce6012010-03-05 10:03:50 +0000898config X86EMU_DEBUG
899 bool "Output verbose x86emu debug messages"
900 default n
901 depends on PCI_OPTION_ROM_RUN_YABEL
902 help
903 This option enables additional x86emu related debug messages.
904
905 Note: This option will increase the size of the coreboot image.
906
907 If unsure, say N.
908
909config X86EMU_DEBUG_JMP
910 bool "Trace JMP/RETF"
911 default n
912 depends on X86EMU_DEBUG
913 help
914 Print information about JMP and RETF opcodes from x86emu.
915
916 Note: This option will increase the size of the coreboot image.
917
918 If unsure, say N.
919
920config X86EMU_DEBUG_TRACE
921 bool "Trace all opcodes"
922 default n
923 depends on X86EMU_DEBUG
924 help
925 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000926
Uwe Hermann01ce6012010-03-05 10:03:50 +0000927 WARNING: This will produce a LOT of output and take a long time.
928
929 Note: This option will increase the size of the coreboot image.
930
931 If unsure, say N.
932
933config X86EMU_DEBUG_PNP
934 bool "Log Plug&Play accesses"
935 default n
936 depends on X86EMU_DEBUG
937 help
938 Print Plug And Play accesses made by option ROMs.
939
940 Note: This option will increase the size of the coreboot image.
941
942 If unsure, say N.
943
944config X86EMU_DEBUG_DISK
945 bool "Log Disk I/O"
946 default n
947 depends on X86EMU_DEBUG
948 help
949 Print Disk I/O related messages.
950
951 Note: This option will increase the size of the coreboot image.
952
953 If unsure, say N.
954
955config X86EMU_DEBUG_PMM
956 bool "Log PMM"
957 default n
958 depends on X86EMU_DEBUG
959 help
960 Print messages related to POST Memory Manager (PMM).
961
962 Note: This option will increase the size of the coreboot image.
963
964 If unsure, say N.
965
966
967config X86EMU_DEBUG_VBE
968 bool "Debug VESA BIOS Extensions"
969 default n
970 depends on X86EMU_DEBUG
971 help
972 Print messages related to VESA BIOS Extension (VBE) functions.
973
974 Note: This option will increase the size of the coreboot image.
975
976 If unsure, say N.
977
978config X86EMU_DEBUG_INT10
979 bool "Redirect INT10 output to console"
980 default n
981 depends on X86EMU_DEBUG
982 help
983 Let INT10 (i.e. character output) calls print messages to debug output.
984
985 Note: This option will increase the size of the coreboot image.
986
987 If unsure, say N.
988
989config X86EMU_DEBUG_INTERRUPTS
990 bool "Log intXX calls"
991 default n
992 depends on X86EMU_DEBUG
993 help
994 Print messages related to interrupt handling.
995
996 Note: This option will increase the size of the coreboot image.
997
998 If unsure, say N.
999
1000config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1001 bool "Log special memory accesses"
1002 default n
1003 depends on X86EMU_DEBUG
1004 help
1005 Print messages related to accesses to certain areas of the virtual
1006 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1007
1008 Note: This option will increase the size of the coreboot image.
1009
1010 If unsure, say N.
1011
1012config X86EMU_DEBUG_MEM
1013 bool "Log all memory accesses"
1014 default n
1015 depends on X86EMU_DEBUG
1016 help
1017 Print memory accesses made by option ROM.
1018 Note: This also includes accesses to fetch instructions.
1019
1020 Note: This option will increase the size of the coreboot image.
1021
1022 If unsure, say N.
1023
1024config X86EMU_DEBUG_IO
1025 bool "Log IO accesses"
1026 default n
1027 depends on X86EMU_DEBUG
1028 help
1029 Print I/O accesses made by option ROM.
1030
1031 Note: This option will increase the size of the coreboot image.
1032
1033 If unsure, say N.
1034
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001035config X86EMU_DEBUG_TIMINGS
1036 bool "Output timing information"
1037 default n
1038 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1039 help
1040 Print timing information needed by i915tool.
1041
1042 If unsure, say N.
1043
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001044config DEBUG_TPM
1045 bool "Output verbose TPM debug messages"
1046 default n
1047 depends on TPM
1048 help
1049 This option enables additional TPM related debug messages.
1050
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001051config DEBUG_SPI_FLASH
1052 bool "Output verbose SPI flash debug messages"
1053 default n
1054 depends on SPI_FLASH
1055 help
1056 This option enables additional SPI flash related debug messages.
1057
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001058config DEBUG_USBDEBUG
1059 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1060 default n
1061 depends on USBDEBUG
1062 help
1063 This option enables additional USB 2.0 debug dongle related messages.
1064
1065 Select this to debug the connection of usbdebug dongle. Note that
1066 you need some other working console to receive the messages.
1067
Stefan Reinauer8e073822012-04-04 00:07:22 +02001068if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1069# Only visible with the right southbridge and loglevel.
1070config DEBUG_INTEL_ME
1071 bool "Verbose logging for Intel Management Engine"
1072 default n
1073 help
1074 Enable verbose logging for Intel Management Engine driver that
1075 is present on Intel 6-series chipsets.
1076endif
1077
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001078config TRACE
1079 bool "Trace function calls"
1080 default n
1081 help
1082 If enabled, every function will print information to console once
1083 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1084 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001085 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001086 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001087
1088config DEBUG_COVERAGE
1089 bool "Debug code coverage"
1090 default n
1091 depends on COVERAGE
1092 help
1093 If enabled, the code coverage hooks in coreboot will output some
1094 information about the coverage data that is dumped.
1095
Uwe Hermann168b11b2009-10-07 16:15:40 +00001096endmenu
1097
Myles Watsond73c1b52009-10-26 15:14:07 +00001098# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001099config ENABLE_APIC_EXT_ID
1100 bool
1101 default n
Myles Watson2e672732009-11-12 16:38:03 +00001102
1103config WARNINGS_ARE_ERRORS
1104 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001105 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001106
Martin Roth77c67b32015-06-25 09:36:27 -06001107# TODO: Remove this when all platforms are fixed.
1108config IASL_WARNINGS_ARE_ERRORS
1109 def_bool y
1110 help
1111 Select to Fail the build if a IASL generates a warning.
1112 This will be defaulted to disabled for the platforms that
1113 currently fail. This allows the REST of the platforms to
1114 have this check enabled while we're working to get those
1115 boards fixed.
1116
1117 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1118 THE ASL.
1119
Peter Stuge51eafde2010-10-13 06:23:02 +00001120# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1121# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1122# mutually exclusive. One of these options must be selected in the
1123# mainboard Kconfig if the chipset supports enabling and disabling of
1124# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1125# in mainboard/Kconfig to know if the button should be enabled or not.
1126
1127config POWER_BUTTON_DEFAULT_ENABLE
1128 def_bool n
1129 help
1130 Select when the board has a power button which can optionally be
1131 disabled by the user.
1132
1133config POWER_BUTTON_DEFAULT_DISABLE
1134 def_bool n
1135 help
1136 Select when the board has a power button which can optionally be
1137 enabled by the user, e.g. when the board ships with a jumper over
1138 the power switch contacts.
1139
1140config POWER_BUTTON_FORCE_ENABLE
1141 def_bool n
1142 help
1143 Select when the board requires that the power button is always
1144 enabled.
1145
1146config POWER_BUTTON_FORCE_DISABLE
1147 def_bool n
1148 help
1149 Select when the board requires that the power button is always
1150 disabled, e.g. when it has been hardwired to ground.
1151
1152config POWER_BUTTON_IS_OPTIONAL
1153 bool
1154 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1155 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1156 help
1157 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001158
1159config REG_SCRIPT
1160 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001161 default n
1162 help
1163 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001164
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001165config MAX_REBOOT_CNT
1166 int
1167 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001168 help
1169 Internal option that sets the maximum number of bootblock executions allowed
1170 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001171 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001172
1173config CBFS_SIZE
1174 hex
1175 default ROM_SIZE
1176 help
1177 This is the part of the ROM actually managed by CBFS. Set it to be
1178 equal to the full rom size if that hasn't been overridden by the
1179 chipset or mainboard.
Lee Leahy10605352016-02-14 17:01:40 -08001180
1181config DEBUG_BOOT_STATE
1182 bool
1183 default n
1184 help
1185 Control debugging of the boot state machine. When selected displays
1186 the state boundaries in ramstage.