blob: eec8f04d3dbf82dcbca7d5abdd48746f9bc50c8b [file] [log] [blame]
Werner Zehfa6f8612016-04-20 10:08:17 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
Werner Zeh0e35eb22017-10-16 08:44:15 +02006 * Copyright (C) 2017 Siemens AG
Werner Zehfa6f8612016-04-20 10:08:17 +02007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <stddef.h>
19#include <soc/romstage.h>
20#include <drivers/intel/fsp1_0/fsp_util.h>
Werner Zeh0e35eb22017-10-16 08:44:15 +020021#include <soc/gpio.h>
22#include "gpio.h"
Werner Zehfa6f8612016-04-20 10:08:17 +020023
24/**
25 * /brief mainboard call for setup that needs to be done before fsp init
26 *
27 */
28void early_mainboard_romstage_entry(void)
29{
Werner Zeh0e35eb22017-10-16 08:44:15 +020030 init_gpios(mc_bdx1_gpio_config);
Werner Zehfa6f8612016-04-20 10:08:17 +020031}
32
33/**
34 * /brief mainboard call for setup that needs to be done after fsp init
35 *
36 */
37void late_mainboard_romstage_entry(void)
38{
39
40}
41
42/**
43 * /brief customize fsp parameters here if needed
44 */
45void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
46{
47
48}