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Mario Scheithauer092db952017-01-31 15:45:13 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010016#include <arch/acpi.h>
Mario Scheithauer092db952017-01-31 15:45:13 +010017DefinitionBlock(
18 "dsdt.aml",
19 "DSDT",
Elyes HAOUAS0cca6e22018-11-13 14:23:29 +010020 0x02, // DSDT revision: ACPI v2.0 and up
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010021 OEM_ID,
22 ACPI_TABLE_CREATOR,
Mario Scheithauer092db952017-01-31 15:45:13 +010023 0x20110725 // OEM revision
24)
25{
Mario Scheithauerd27a5652017-07-17 14:31:41 +020026 /* generic macros */
27 #include <soc/intel/apollolake/acpi/platform.asl>
28
Mario Scheithauer092db952017-01-31 15:45:13 +010029 /* global NVS and variables */
30 #include <soc/intel/apollolake/acpi/globalnvs.asl>
31
32 /* CPU */
33 #include <soc/intel/apollolake/acpi/cpu.asl>
34
35 Scope (\_SB) {
36 Device (PCI0)
37 {
38 #include <soc/intel/apollolake/acpi/northbridge.asl>
39 #include <soc/intel/apollolake/acpi/southbridge.asl>
40 #include <soc/intel/apollolake/acpi/pch_hda.asl>
41 }
42 }
43
44 /* Chipset specific sleep states */
45 #include <soc/intel/apollolake/acpi/sleepstates.asl>
46}