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Stefan Reinauer23190272008-08-20 13:41:24 +00001/*
2 * inteltool - dump all registers on an Intel CPU + chipset based system.
3 *
4 * Copyright (C) 2008 by coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <stdio.h>
Stefan Reinauer23190272008-08-20 13:41:24 +000021#include "inteltool.h"
22
23static const io_register_t ich0_gpio_registers[] = {
24 { 0x00, 4, "GPIO_USE_SEL" },
25 { 0x04, 4, "GP_IO_SEL" },
26 { 0x08, 4, "RESERVED" },
27 { 0x0c, 4, "GP_LVL" },
28 { 0x10, 4, "RESERVED" },
29 { 0x14, 4, "GPO_TTL" },
30 { 0x18, 4, "GPO_BLINK" },
31 { 0x1c, 4, "RESERVED" },
32 { 0x20, 4, "RESERVED" },
33 { 0x24, 4, "RESERVED" },
34 { 0x28, 4, "RESERVED" },
35 { 0x2c, 4, "GPI_INV" },
36 { 0x30, 4, "RESERVED" },
37 { 0x34, 4, "RESERVED" },
38 { 0x38, 4, "RESERVED" },
39 { 0x3C, 4, "RESERVED" }
40};
41
42static const io_register_t ich4_gpio_registers[] = {
43 { 0x00, 4, "GPIO_USE_SEL" },
44 { 0x04, 4, "GP_IO_SEL" },
45 { 0x08, 4, "RESERVED" },
46 { 0x0c, 4, "GP_LVL" },
47 { 0x10, 4, "RESERVED" },
48 { 0x14, 4, "GPO_TTL" },
49 { 0x18, 4, "GPO_BLINK" },
50 { 0x1c, 4, "RESERVED" },
51 { 0x20, 4, "RESERVED" },
52 { 0x24, 4, "RESERVED" },
53 { 0x28, 4, "RESERVED" },
54 { 0x2c, 4, "GPI_INV" },
55 { 0x30, 4, "GPIO_USE_SEL2" },
56 { 0x34, 4, "GP_IO_SEL2" },
57 { 0x38, 4, "GP_LVL2" },
58 { 0x3C, 4, "RESERVED" }
59};
60
61static const io_register_t ich7_gpio_registers[] = {
62 { 0x00, 4, "GPIO_USE_SEL" },
63 { 0x04, 4, "GP_IO_SEL" },
64 { 0x08, 4, "RESERVED" },
65 { 0x0c, 4, "GP_LVL" },
66 { 0x10, 4, "RESERVED" },
67 { 0x14, 4, "RESERVED" },
68 { 0x18, 4, "GPO_BLINK" },
69 { 0x1c, 4, "RESERVED" },
70 { 0x20, 4, "RESERVED" },
71 { 0x24, 4, "RESERVED" },
72 { 0x28, 4, "RESERVED" },
73 { 0x2c, 4, "GPI_INV" },
74 { 0x30, 4, "GPIO_USE_SEL2" },
75 { 0x34, 4, "GP_IO_SEL2" },
76 { 0x38, 4, "GP_LVL2" },
77 { 0x3C, 4, "RESERVED" }
78};
79
Stefan Reinauer1162f252008-12-04 15:18:20 +000080static const io_register_t ich8_gpio_registers[] = {
81 { 0x00, 4, "GPIO_USE_SEL" },
82 { 0x04, 4, "GP_IO_SEL" },
83 { 0x08, 4, "RESERVED" },
84 { 0x0c, 4, "GP_LVL" },
85 { 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
86 { 0x14, 4, "RESERVED" },
87 { 0x18, 4, "GPO_BLINK" },
88 { 0x1c, 4, "GP_SER_BLINK" },
89 { 0x20, 4, "GP_SB_CMDSTS" },
90 { 0x24, 4, "GP_SB_DATA" },
91 { 0x28, 4, "RESERVED" },
92 { 0x2c, 4, "GPI_INV" },
93 { 0x30, 4, "GPIO_USE_SEL2" },
94 { 0x34, 4, "GP_IO_SEL2" },
95 { 0x38, 4, "GP_LVL2" },
96 { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
97};
98
99
Stefan Reinauer23190272008-08-20 13:41:24 +0000100int print_gpios(struct pci_dev *sb)
101{
102 int i, size;
103 uint16_t gpiobase;
104 const io_register_t *gpio_registers;
105
106 printf("\n============= GPIOS =============\n\n");
107
108 switch (sb->device_id) {
Stefan Reinauer1162f252008-12-04 15:18:20 +0000109 case PCI_DEVICE_ID_INTEL_ICH8M:
110 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
111 gpio_registers = ich8_gpio_registers;
112 size = ARRAY_SIZE(ich8_gpio_registers);
113 break;
Stefan Reinauer23190272008-08-20 13:41:24 +0000114 case PCI_DEVICE_ID_INTEL_ICH7:
115 case PCI_DEVICE_ID_INTEL_ICH7M:
116 case PCI_DEVICE_ID_INTEL_ICH7DH:
117 case PCI_DEVICE_ID_INTEL_ICH7MDH:
118 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
119 gpio_registers = ich7_gpio_registers;
120 size = ARRAY_SIZE(ich7_gpio_registers);
121 break;
122 case PCI_DEVICE_ID_INTEL_ICH4:
123 case PCI_DEVICE_ID_INTEL_ICH4M:
124 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
125 gpio_registers = ich4_gpio_registers;
126 size = ARRAY_SIZE(ich4_gpio_registers);
127 break;
128 case PCI_DEVICE_ID_INTEL_ICH:
129 case PCI_DEVICE_ID_INTEL_ICH0:
130 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
131 gpio_registers = ich0_gpio_registers;
132 size = ARRAY_SIZE(ich0_gpio_registers);
133 break;
134 case 0x1234: // Dummy for non-existent functionality
135 printf("This southbridge does not have GPIOBASE.\n");
136 return 1;
137 default:
138 printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
139 return 1;
140 }
141
142 printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
143
144 for (i = 0; i < size; i++) {
145 switch (gpio_registers[i].size) {
146 case 4:
147 printf("gpiobase+0x%04x: 0x%08x (%s)\n",
148 gpio_registers[i].addr,
149 inl(gpiobase+gpio_registers[i].addr),
150 gpio_registers[i].name);
151 break;
152 case 2:
153 printf("gpiobase+0x%04x: 0x%04x (%s)\n",
154 gpio_registers[i].addr,
155 inw(gpiobase+gpio_registers[i].addr),
156 gpio_registers[i].name);
157 break;
158 case 1:
159 printf("gpiobase+0x%04x: 0x%02x (%s)\n",
160 gpio_registers[i].addr,
161 inb(gpiobase+gpio_registers[i].addr),
162 gpio_registers[i].name);
163 break;
164 }
165 }
166
167 return 0;
168}
169