/* SPDX-License-Identifier: BSD-3-Clause */

//-----------------------------------------------------------------------------
// Include files
//-----------------------------------------------------------------------------
#include "dramc_common.h"
#include "dramc_int_global.h"
#include "x_hal_io.h"
//-----------------------------------------------------------------------------
// Global variables
//-----------------------------------------------------------------------------
U8 gDRSEnableSelfWakeup = 0;

#if (CHECK_GOLDEN_SETTING == TRUE)
typedef struct _GOLDEN_FIELD_T
{
    char fieldName[64];
    U32 group;
    U32 field;
    U32 u4ChaValue;
} GOLDEN_FIELD_T;
GOLDEN_FIELD_T *golden_setting_anwer;

#if APPLY_LOWPOWER_GOLDEN_SETTINGS

GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
{
    {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0},
    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x0},
    {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x334f3000},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
    {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x0},
    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0},
    {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x0},
    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0},
    {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0},
    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0},
    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0},
    {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x0},
    {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0},
    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0},
    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x0},
    {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0},
    {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0},
    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
    {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x0},
    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x0},
    {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0},
    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0},
    {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0},
    {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0},
    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
    {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1},
    {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
    {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
};

GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
{
    {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x0},
    {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1},
    {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0},
    {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
    {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
    {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x0},
    {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
    {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
    {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0},
    {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x0},
    {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
    {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0},
    {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
    {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0},
    {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0},
    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x0},
    {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x0},
    {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x0},
    {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0},
    {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x0},
    {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x1},
    {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1},
    {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x0},
    {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
    {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x1},
    {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0},
    {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0},
    {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x0},
    {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
    {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x1},
    {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x1},
    {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1},
    {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
    {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0},
    {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
    {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x1},
    {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
    {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0},
    {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x1},
    {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1},
    {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1},
    {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0},
    {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
    {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x0},
    {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0},
    {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0},
    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x1},
    {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x0},
    {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0},
    {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
    {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
    {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
    {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x0},
    {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0},
    {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0},
    {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
    {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x0},
    {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1},
    {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0},
    {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
    {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
    {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0},
    {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x0},
    {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
    {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x0},
    {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0},
    {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1},
    {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x0},
    {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
    {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x0},
    {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0},
    {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1},
    {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x0},
    {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x1},
};

#else

GOLDEN_FIELD_T shuf_golden_setting_anwer[] =
{
    {"SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x1},
    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 0x1},
    {"MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL", DDRPHY_REG_MISC_SHU_CG_CTRL0, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 0x11400000},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0},
    {"SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1},
    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 0x1},
    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x1},
    {"SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 0x1},
    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0},
    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x1},
    {"SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x1},
    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x1},
    {"SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x1},
    {"SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 0x1},
    {"SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x1},
    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x1},
    {"SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 0x1},
    {"SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x1},
    {"SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1},
    {"SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x1},
    {"SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
    {"SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 0x1},
    {"SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA", DDRPHY_REG_SHU_CA_CMD8, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 0x1},
    {"SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1},
    {"SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW", DDRPHY_REG_SHU_CA_CMD7, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0},
    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x1},
    {"SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x1},
    {"SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA", DDRPHY_REG_SHU_CA_CMD13, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0},
    {"SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x1},
    {"SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x1},
    {"SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x1},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0},
    {"SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1", DDRPHY_REG_SHU_B1_DQ7, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0},
    {"SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT", DRAMC_REG_SHU_APHY_TX_PICG_CTRL, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x0},
    {"SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0", DDRPHY_REG_SHU_B0_DQ8, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x1},
    {"SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0", DDRPHY_REG_SHU_B0_DQ7, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0},
    {"SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1", DDRPHY_REG_SHU_B1_DQ8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1},
};

GOLDEN_FIELD_T nonshuf_golden_setting_anwer[] =
{
    {"SCSMCTRL_CG_SCARB_SM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCARB_SM_CGAR, 0x1},
    {"MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0},
    {"MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1},
    {"MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0},
    {"DUMMY_RD_DUMMY_RD_PA_OPT", DRAMC_REG_DUMMY_RD, DUMMY_RD_DUMMY_RD_PA_OPT, 0x1},
    {"DVFS_CTRL0_DVFS_CG_OPT", DRAMC_REG_DVFS_CTRL0, DVFS_CTRL0_DVFS_CG_OPT, 0x1},
    {"MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0},
    {"MISC_CTRL3_ARPI_CG_MCTL_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQSIEN", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0},
    {"MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1},
    {"RX_CG_SET0_RDATCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDATCKAR, 0x1},
    {"MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0},
    {"MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1},
    {"MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0},
    {"MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1},
    {"MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1},
    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE, 0x1},
    {"RX_CG_SET0_RDYCKAR", DRAMC_REG_RX_CG_SET0, RX_CG_SET0_RDYCKAR, 0x1},
    {"DDRCOMMON0_DISSTOP26M", DRAMC_REG_DDRCOMMON0, DDRCOMMON0_DISSTOP26M, 0x1},
    {"MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS", DRAMC_REG_MISCTL0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1},
    {"DCM_CTRL0_BCLKAR", DRAMC_REG_DCM_CTRL0, DCM_CTRL0_BCLKAR, 0x1},
    {"DRAMC_PD_CTRL_DCMEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN, 0x0},
    {"MISC_CG_CTRL5_R_CA_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0},
    {"CLKAR_REQQUECLKRUN", DRAMC_REG_CLKAR, CLKAR_REQQUECLKRUN, 0x1},
    {"CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT", DDRPHY_REG_CA_DLL_ARPI1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0},
    {"DRAMC_PD_CTRL_DCMENNOTRFC", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMENNOTRFC, 0x0},
    {"MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN", DDRPHY_REG_MISC_DUTYSCAN1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1},
    {"TX_TRACKING_SET0_HMRRSEL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1},
    {"ACTIMING_CTRL_SEQCLKRUN", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN, 0x1},
    {"MISC_CTRL3_ARPI_CG_CLK_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0},
    {"CMD_DEC_CTRL0_SELPH_CMD_CG_DIS", DRAMC_REG_CMD_DEC_CTRL0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1},
    {"MISC_CTRL4_R_OPT2_CG_DQS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQS, 0x0},
    {"TX_TRACKING_SET0_RDDQSOSC_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1},
    {"MISC_CTRL4_R_OPT2_CG_CMD", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CMD, 0x0},
    {"DRAMC_PD_CTRL_PHYCLKDYNGEN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0},
    {"MISC_CTRL3_ARPI_CG_MCK_CA_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0},
    {"DRAMC_PD_CTRL_COMBPHY_CLKENSAME", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1},
    {"MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0},
    {"MISC_CTRL3_ARPI_CG_CMD_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_DQ", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQ, 0x0},
    {"MISC_CTRL3_ARPI_CG_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0},
    {"MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1},
    {"DRAMC_PD_CTRL_COMBCLKCTRL", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_COMBCLKCTRL, 0x0},
    {"MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0},
    {"MISC_CG_CTRL5_R_CA_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0},
    {"MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1},
    {"MISC_CTRL3_ARPI_CG_DQS_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0},
    {"TX_CG_SET0_TX_ATK_CLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_TX_ATK_CLKRUN, 0x1},
    {"ZQ_SET0_ZQCS_MASK_SEL_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1},
    {"DRAMC_PD_CTRL_APHYCKCG_FIXOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1},
    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0},
    {"MISC_CTRL4_R_OPT2_CG_CS", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CS, 0x0},
    {"MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0},
    {"MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE, 0x1},
    {"MISC_CTRL3_R_DDRPHY_COMB_CG_IG", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1},
    {"MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0},
    {"DRAMC_PD_CTRL_DCMEN2", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_DCMEN2, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1},
    {"MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0},
    {"MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1},
    {"MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5},
    {"SCSMCTRL_CG_SCSM_CGAR", DRAMC_REG_SCSMCTRL_CG, SCSMCTRL_CG_SCSM_CGAR, 0x1},
    {"DRAMC_PD_CTRL_MIOCKCTRLOFF", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1},
    {"MISC_CTRL4_R_OPT2_CG_CLK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_CLK, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1},
    {"MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1},
    {"ACTIMING_CTRL_SEQCLKRUN3", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN3, 0x1},
    {"ACTIMING_CTRL_SEQCLKRUN2", DRAMC_REG_ACTIMING_CTRL, ACTIMING_CTRL_SEQCLKRUN2, 0x1},
    {"MISC_CG_CTRL5_R_DQ0_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0},
    {"MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN", DDRPHY_REG_MISC_RX_AUTOK_CFG0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1},
    {"MISC_CTRL3_ARPI_CG_MCK_DQ_OPT", DDRPHY_REG_MISC_CTRL3, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0},
    {"MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0},
    {"MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1},
    {"TX_CG_SET0_DWCLKRUN", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_DWCLKRUN, 0x1},
    {"MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1},
    {"SREF_DPD_CTRL_SREF_CG_OPT", DRAMC_REG_SREF_DPD_CTRL, SREF_DPD_CTRL_SREF_CG_OPT, 0x1},
    {"TX_TRACKING_SET0_TXUIPI_CAL_CGAR", DRAMC_REG_TX_TRACKING_SET0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1},
    {"MISC_CTRL4_R_OPT2_MPDIV_CG", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0},
    {"TX_CG_SET0_WDATA_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_WDATA_CG_DIS, 0x1},
    {"MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE", DDRPHY_REG_MISC_CG_CTRL0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1},
    {"MISC_CTRL4_R_OPT2_CG_MCK", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_MCK, 0x0},
    {"MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3},
    {"MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL", DDRPHY_REG_MISC_CG_CTRL2, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17},
    {"TX_CG_SET0_SELPH_CG_DIS", DRAMC_REG_TX_CG_SET0, TX_CG_SET0_SELPH_CG_DIS, 0x1},
    {"DRAMC_PD_CTRL_PHYGLUECLKRUN", DRAMC_REG_DRAMC_PD_CTRL, DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1},
    {"MISC_CG_CTRL5_R_DQ1_PI_DCM_EN", DDRPHY_REG_MISC_CG_CTRL5, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0},
    {"CLKAR_REQQUE_PACG_DIS", DRAMC_REG_CLKAR, CLKAR_REQQUE_PACG_DIS, 0x7fff},
    {"ZQ_SET0_ZQMASK_CGAR", DRAMC_REG_ZQ_SET0, ZQ_SET0_ZQMASK_CGAR, 0x1},
    {"MISC_CTRL4_R_OPT2_CG_DQM", DDRPHY_REG_MISC_CTRL4, MISC_CTRL4_R_OPT2_CG_DQM, 0x0},
};

#endif
#endif

static void EnableCommonDCMNonShuffle(DRAMC_CTX_T *p)
{
    vIO32WriteFldAlign_All(DRAMC_REG_ACTIMING_CTRL, 0x1, ACTIMING_CTRL_SEQCLKRUN3);
    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
            P_Fld(0x1, MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE) |
            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN) |
            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF) |
            P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF));
    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
            P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE) |
            P_Fld(0x17, MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL) |
            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FSEL) |
            P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27) |
            P_Fld(0x3, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL) |
            P_Fld(0x0, MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30) |
            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF) |
            P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN) |
            P_Fld(0x0, MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE) |
            P_Fld(0x0, MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE) |
            P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG) |
            P_Fld(0x5, MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT));

    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
    vIO32WriteFldAlign_All(DDRPHY_REG_CA_DLL_ARPI1, 0x0, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);
    vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQS_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_DQ_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_CMD_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCTL_CA_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_CLK_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT) |
            P_Fld(0x0, MISC_CTRL3_ARPI_CG_MCK_CA_OPT));
return;
}

static void EnableCommonDCMShuffle(DRAMC_CTX_T *p)
{
    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;

    if((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) && (isLP4_DSC))
    {
        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0x1, SHU_B1_DQ12_DMY_DQ12_B1);  
    }
    else
    {
        vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ12, 0, SHU_B1_DQ12_DMY_DQ12_B1);  
    }

    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
            P_Fld(!isLP4_DSC, SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1) |
            P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1));
    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD7,
            P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW) |
            P_Fld(0x0, SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW));
    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ7,
            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1) |
            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1) |
            P_Fld(0x0, SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1));
    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x0, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA);
    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
            P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0) |
            P_Fld(0x1, SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0));
#if TX_PICG_NEW_MODE  
    vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ7,
            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0) |
            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0) |
            P_Fld(0x0, SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0));
#endif
return;
}

void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn)
{
    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
    U8 MPDIV_CG = 1;

    EnableCommonDCMNonShuffle(p);

    if(bEn)
    {
        vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x0, SREF_DPD_CTRL_SREF_CG_OPT);
        vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
                P_Fld(0x0, RX_CG_SET0_RDYCKAR) |
                P_Fld(0x0, RX_CG_SET0_RDATCKAR));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
                P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
                P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));

        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
        vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
                P_Fld(0x0, TX_CG_SET0_DWCLKRUN) |
                P_Fld(0x0, TX_CG_SET0_SELPH_CG_DIS) |
                P_Fld(0x0, TX_CG_SET0_TX_ATK_CLKRUN) |
                P_Fld(0x0, TX_CG_SET0_WDATA_CG_DIS));
        vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
                P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN2) |
                P_Fld(0x0, ACTIMING_CTRL_SEQCLKRUN));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
                P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x0, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
        vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x0, DDRCOMMON0_DISSTOP26M);
        vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
                P_Fld(0x0, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
                P_Fld(0x0, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
                P_Fld(0x0, TX_TRACKING_SET0_HMRRSEL_CGAR));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x0, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
                P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
                P_Fld(0x1, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
                P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
                P_Fld(0x1, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
                P_Fld(0x1, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
                P_Fld(0x1, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
                P_Fld(0x0, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
                P_Fld(0x0, ZQ_SET0_ZQMASK_CGAR));
        vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x0, DVFS_CTRL0_DVFS_CG_OPT);
        vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x0, DCM_CTRL0_BCLKAR);
        vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
                P_Fld(0x0, SCSMCTRL_CG_SCARB_SM_CGAR) |
                P_Fld(0x0, SCSMCTRL_CG_SCSM_CGAR));
        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
                P_Fld(0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
                P_Fld(0x1, DRAMC_PD_CTRL_DCMEN2) |
                P_Fld(0x1, DRAMC_PD_CTRL_DCMEN) |
                P_Fld(0x0, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
                P_Fld(0x0, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
                P_Fld(0x0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
                P_Fld(0x0, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
                P_Fld(0x1, DRAMC_PD_CTRL_DCMENNOTRFC) |
                P_Fld(0x1, DRAMC_PD_CTRL_COMBCLKCTRL));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
                P_Fld(0x0, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
                P_Fld(0x0, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
        vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x0, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
        vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x0, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
#if ENABLE_DDR800_SOPEN_DSC_WA
        if (isLP4_DSC&&(vGet_DDR_Loop_Mode(p)==SEMI_OPEN_LOOP_MODE))
            MPDIV_CG = 0;
#endif
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
#if (RX_PICG_NEW_MODE || TX_PICG_NEW_MODE)
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_MCK) |
                P_Fld(MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG) |
#endif
#if RX_PICG_NEW_MODE     
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
#endif
#if TX_PICG_NEW_MODE   
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQ)  |
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQS) |
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_DQM) |
#endif
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CMD) |
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CLK) |
                P_Fld(0x1, MISC_CTRL4_R_OPT2_CG_CS));
        vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
                P_Fld(0x0, CLKAR_REQQUE_PACG_DIS) |
                P_Fld(0x0, CLKAR_REQQUECLKRUN));
    }
    else
    {
        vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0x1, SREF_DPD_CTRL_SREF_CG_OPT);
        vIO32WriteFldMulti_All(DRAMC_REG_RX_CG_SET0,
                P_Fld(0x1, RX_CG_SET0_RDYCKAR) |
                P_Fld(0x1, RX_CG_SET0_RDATCKAR));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL2,
                P_Fld(0x1, MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON) |
                P_Fld(0x0, MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN));

        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 1, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0, MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG);
        vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0,
                P_Fld(0x1, TX_CG_SET0_DWCLKRUN) |
                P_Fld(0x1, TX_CG_SET0_SELPH_CG_DIS) |
                P_Fld(0x1, TX_CG_SET0_TX_ATK_CLKRUN) |
                P_Fld(0x1, TX_CG_SET0_WDATA_CG_DIS));
        vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL,
                P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN2) |
                P_Fld(0x1, ACTIMING_CTRL_SEQCLKRUN));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB0_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_TX_OLD_DCM_COMB1_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
                P_Fld(0x1, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0x1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN);
        vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 0x1, DDRCOMMON0_DISSTOP26M);
        vIO32WriteFldMulti_All(DRAMC_REG_TX_TRACKING_SET0,
                P_Fld(0x1, TX_TRACKING_SET0_TXUIPI_CAL_CGAR) |
                P_Fld(0x1, TX_TRACKING_SET0_RDDQSOSC_CGAR) |
                P_Fld(0x1, TX_TRACKING_SET0_HMRRSEL_CGAR));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 0x1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5,
                P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
                P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN) |
                P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
                P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
                P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
                P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN));
        vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0,
                P_Fld(0x1, ZQ_SET0_ZQCS_MASK_SEL_CGAR) |
                P_Fld(0x1, ZQ_SET0_ZQMASK_CGAR));
        vIO32WriteFldAlign_All(DRAMC_REG_DVFS_CTRL0, 0x1, DVFS_CTRL0_DVFS_CG_OPT);
        vIO32WriteFldAlign_All(DRAMC_REG_DCM_CTRL0, 0x1, DCM_CTRL0_BCLKAR);
        vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG,
                P_Fld(0x1, SCSMCTRL_CG_SCARB_SM_CGAR) |
                P_Fld(0x1, SCSMCTRL_CG_SCSM_CGAR));
        vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL,
                P_Fld(0x0, DRAMC_PD_CTRL_PHYCLKDYNGEN) |
                P_Fld(0x0, DRAMC_PD_CTRL_DCMEN2) |
                P_Fld(0x0, DRAMC_PD_CTRL_DCMEN) |
                P_Fld(0x1, DRAMC_PD_CTRL_PHYGLUECLKRUN) |
                P_Fld(0x1, DRAMC_PD_CTRL_COMBPHY_CLKENSAME) |
                P_Fld(0x1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) |
                P_Fld(0x1, DRAMC_PD_CTRL_MIOCKCTRLOFF) |
                P_Fld(0x0, DRAMC_PD_CTRL_DCMENNOTRFC) |
                P_Fld(0x0, DRAMC_PD_CTRL_COMBCLKCTRL));
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3,
                P_Fld(0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG) |
                P_Fld(0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG));
        vIO32WriteFldAlign_All(DRAMC_REG_CMD_DEC_CTRL0, 0x1, CMD_DEC_CTRL0_SELPH_CMD_CG_DIS);
        vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
        vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4,
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQSIEN) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CLK) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_MPDIV_CG) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQM) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CMD) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQS) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_MCK) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_CS) |
                P_Fld(0x0, MISC_CTRL4_R_OPT2_CG_DQ));
        vIO32WriteFldMulti_All(DRAMC_REG_CLKAR,
                P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS) |
                P_Fld(0x1, CLKAR_REQQUECLKRUN));
    }
    return;
}

void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn)
{
    BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;

    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND3: Special case
    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND2: Special case
    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_READ_START_EXTEND1: Special case
    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND1: Special case
    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND2: Special case
    // DRAMC_REG_SHU_RX_CG_SET0 - SHU_RX_CG_SET0_DLE_LAST_EXTEND3: Special case
    EnableCommonDCMShuffle(p);

    if(bEn)
    {
#if TX_PICG_NEW_MODE 
        vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x1, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
#endif
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
                P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
                P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
                P_Fld(0x0, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
                P_Fld(0x0, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
                P_Fld(isLP4_DSC, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x334f3000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
                P_Fld(0x0, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
    }
    else
    {
        vIO32WriteFldAlign_All(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT);
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8,
                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1) |
                P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1));
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD8,
                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA) |
                P_Fld(0x1, SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA));
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_CG_CTRL0, 0x11400000, MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL);
        vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8,
                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0) |
                P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0));
    }
    return;
}



void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
{
    U32 u4WbrBackup = GetDramcBroadcast();
    DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);

    EnableDramcPhyDCMNonShuffle(p, bEn);
    EnableDramcPhyDCMShuffle(p, bEn);

#if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0))
    DRAM_STATUS_T stResult = CheckGoldenSetting(p);
    mcSHOW_DBG_MSG3(("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
#endif

    DramcBroadcastOnOff(u4WbrBackup);
    return;
}


#if RX_PICG_NEW_MODE
#if 0
DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p)
{
    U8 channel_idx;
    U8 u1RankIdx;
    U32 u4Value;


    for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
    {
        p->channel = channel_idx;
        mcSHOW_DBG_MSG(("CH[%d] \n", channel_idx));        
        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_MCK);
        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_MPDIV_CG);
        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_DQSIEN);
        mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value));                                


        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), MISC_STBCAL1_STBCNT_SHU_RST_EN);
        mcSHOW_DBG_MSG(("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
        mcSHOW_DBG_MSG(("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
        mcSHOW_DBG_MSG(("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value));                                
        
        
        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
        mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value));                                

        for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
        {
            
            vSetRank(p, u1RankIdx);
            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT);    
            mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value));                                
            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT);
            mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value));                                
        }
        vSetRank(p, RANK_0);        

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value));                                
        
        
        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value));                                

        u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN);
        mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value));                                

    }
    p->channel = CHANNEL_A;
}
#endif
#endif

#if (CHECK_GOLDEN_SETTING == TRUE)
static DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_anwer, U16 array_size)
{
    DRAM_STATUS_T eStatus = DRAM_OK;
    U8 channel_idx;
    U32 u4Value = 0;
    U32 u4Answer = 0;
    U16 array_cnt = array_size / sizeof(golden_setting_anwer[0]);

    U16 u2Idx = 0;
    for(u2Idx = 0; u2Idx < array_cnt; u2Idx++)
    {
        for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
        {
            vSetPHY2ChannelMapping(p, channel_idx);
            u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field);
            //mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value));
        
            u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);

            if(u4Answer != 0xffffffff)
            {
                if(u4Answer == u4Value)
                {
                    //mcSHOW_DBG_MSG(("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer));
                }
                else
                {
                    mcSHOW_ERR_MSG(("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer));           
                    eStatus |= DRAM_FAIL;
                }
            }
        }
    }
    return eStatus;
}

DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
{
    U8 u1BkShuffleIdx = vGet_Current_SRAMIdx(p);
    U8 u1SramShuffleIdx = 0;
    U8 u1ShuffleIdx = 0;
    U8 backup_channel = vGetPHY2ChannelMapping(p);
    DRAM_STATUS_T eStatus = DRAM_OK;

    mcSHOW_DBG_MSG3(("Golden setting check[Begin]\n"));
    eStatus |= CheckGoldenField(p, nonshuf_golden_setting_anwer, sizeof(nonshuf_golden_setting_anwer));


    if(gAndroid_DVFS_en)
    {
        for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
        {
            if (u1ShuffleIdx < DRAM_DFS_SRAM_MAX)
            {
                mcSHOW_DBG_MSG3(("SRAM SHU%d\n", u1ShuffleIdx));
                u1SramShuffleIdx = u1ShuffleIdx;
            }
            else
            {
                mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
                u1SramShuffleIdx = u1BkShuffleIdx;
            }

            //mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n",  sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0])));
            DramcDFSDirectJump(p, u1SramShuffleIdx);
            DramcDFSDirectJump(p, u1SramShuffleIdx);

            eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
        }
    }
    else
    {
        mcSHOW_DBG_MSG3(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
        eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
    }

    mcSHOW_DBG_MSG3(("Golden setting check[End]\n"));

    vSetPHY2ChannelMapping(p, backup_channel);
    return eStatus;
}
#endif


void HwSaveForSR(DRAMC_CTX_T *p)
{
    vIO32WriteFldMulti_All(DRAMC_REG_SREF_DPD_CTRL, P_Fld(0, SREF_DPD_CTRL_GT_SYNC_MASK)
                | P_Fld(1, SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN)
                | P_Fld(1, SREF_DPD_CTRL_SREF2_OPTION)                        
                | P_Fld(0, SREF_DPD_CTRL_SREF3_OPTION));

    vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x0, MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY);
}
//#endif


//#ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL

void ClkFreeRunForDramcPsel(DRAMC_CTX_T *p)
{
    vIO32WriteFldMulti_All(DRAMC_REG_TX_CG_SET0, P_Fld(0, TX_CG_SET0_PSEL_OPT1)
            | P_Fld(0, TX_CG_SET0_PSEL_OPT2)
            | P_Fld(0, TX_CG_SET0_PSEL_OPT3)
            | P_Fld(0, TX_CG_SET0_PSELAR));
}
//#endif

#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
#if 0
static void EnableDllCg(DRAMC_CTX_T *p, U32 u4OnOff)
{
    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI2, u4OnOff, SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0);
    vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL_ARPI2, u4OnOff, SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1);
    vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_DLL_ARPI2 + SHIFT_TO_CHB_ADDR, u4OnOff, SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA);
}
#endif
void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
{
#if __Petrus_TO_BE_PORTING__
    U8 u1ShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_MISC_DVFSCTL, MISC_DVFSCTL_R_OTHER_SHU_GP);
    U8 u1IsDdr800Semi = u4IO32ReadFldAlign(DDRPHY_REG_SHU_PLL1 + (SHU_GRP_DDRPHY_OFFSET * u1ShuLevel), SHU_PLL1_RG_RPHYPLL_DDR400_EN);

    if (u1IsDdr800Semi != 1)
        return;

    if ((next_shu_level != SRAM_SHU9) && (u1OnOff == DISABLE))
    {

        EnableDllCg(p, DISABLE);
    }
    else if ((next_shu_level == SRAM_SHU9) && (u1OnOff == ENABLE))
    {

        EnableDllCg(p, ENABLE);
    }
#endif
}
#endif
#if 0
void DramcDRS(DRAMC_CTX_T *p, U8 bEnable)
{

    vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DRSCTRL), P_Fld(0, DRSCTRL_DRSPB2AB_OPT)
                                                            | P_Fld(0, DRSCTRL_DRSMON_CLR)
                                                            | P_Fld(8, DRSCTRL_DRSDLY)
                                                            | P_Fld(0, DRSCTRL_DRSACKWAITREF)
                                                            | P_Fld(!bEnable, DRSCTRL_DRSDIS)
                                                            | P_Fld(1, DRSCTRL_DRSCLR_EN)
                                                            | P_Fld(3, DRSCTRL_DRS_CNTX)
                                                            | P_Fld(!gDRSEnableSelfWakeup, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS)
                                                            | P_Fld(0, DRSCTRL_DRSOPT2));
}
#endif

#if 0
#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
{
    U8 ucstatus = 0;
    U32 uiTemp;
    U32 u4TimeCnt;

    u4TimeCnt = TIME_OUT_CNT;

    mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit")));

    if (op == 1)
    {

        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SRFPD_DIS);

        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 1, SREFCTRL_SELFREF);
        mcDELAY_US(2);
        uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
        while ((uiTemp == 0) && (u4TimeCnt > 0))
        {
            mcSHOW_DBG_MSG2(("Still not enter self refresh(%d)\n", u4TimeCnt));
            mcDELAY_US(1);
            uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
            u4TimeCnt --;
        }
    }
    else
    {
        vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SREFCTRL), 0, SREFCTRL_SELFREF);

        mcDELAY_US(2);
        uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
        while ((uiTemp != 0) && (u4TimeCnt > 0))
        {
            mcSHOW_DBG_MSG2(("Still not exit self refresh(%d)\n", u4TimeCnt));
            mcDELAY_US(1);
            uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
            u4TimeCnt--;
        }
    }

   if (u4TimeCnt == 0)
   {
        mcSHOW_DBG_MSG(("Self refresh fail\n"));
   }
   else
   {
        mcSHOW_DBG_MSG(("Self refresh done\n"));
   }
}
#endif
#endif

//#if ENABLE_RX_DCM_DPHY
void EnableRxDcmDPhy(DRAMC_CTX_T *p, U16 u2Freq)
{
    U8 u1PRECAL_CG_EN = 0;


    if (u1IsPhaseMode(p) == TRUE)
        u1PRECAL_CG_EN = 1;
    else
        u1PRECAL_CG_EN = 0;


    vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL,
            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT) |
            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT) |
            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT) |
            P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN) |
            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN) |
            P_Fld(0x1, MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN) |
            P_Fld(u1PRECAL_CG_EN, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN) |
            P_Fld(0x2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY) |
            P_Fld(0x0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY));

#if RDSEL_TRACKING_EN 
    if(u2Freq >= RDSEL_TRACKING_TH)
    {
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x0, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
    }
    else
    #endif
    {
        vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, 0x1, MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN);
    }

}
//#endif

//#if CMD_PICG_NEW_MODE 
void EnableCmdPicgEffImprove(DRAMC_CTX_T *p)
{
    U16 u2Clk_Dyn_Gating_Sel = 0x4;

    if (vGet_Div_Mode(p) == DIV4_MODE)
    {
        u2Clk_Dyn_Gating_Sel = 0x6;
    }
    else
    {
        u2Clk_Dyn_Gating_Sel = 0x5;
    }

    vIO32WriteFldMulti(DRAMC_REG_SHU_DCM_CTRL0, P_Fld(1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT) | P_Fld(u2Clk_Dyn_Gating_Sel, SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL));
}
//#endif
