mb/google/sarien: Enable LAN clock source usage

FSP defined a special clock source usage 0x70 for PCH LAN device, update
that to google sarien platform.

BUG=b:120003760
TEST=Boot up into OS, ethernet able to be listed in ifconfig.

Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 93e0af9..fccec9f 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -80,7 +80,7 @@
 
 	# PCIe port 9 for LAN
 	register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[0]" = "8"
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe port 10 for M.2 2230 WLAN
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index d25e725..49200ad 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -85,7 +85,7 @@
 
 	# PCIe port 9 for LAN
 	register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[3]" = "8"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# PCIe port 10 for M.2 2230 WLAN