diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 5cf24b2..145526a 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -32,7 +32,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <tpm.h>
@@ -40,7 +39,7 @@
 
 #define SIO_PORT 0x164e
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	device_t dev = PCH_LPC_DEV;
 
@@ -64,7 +63,7 @@
 	}
 }
 
-static void rcba_config(void)
+void rcba_config(void)
 {
 	u32 reg32;
 
@@ -76,19 +75,7 @@
 	RCBA32(FD) = reg32;
 }
 
-// FIXME, this function is generic code that should go to sb/... or
-// nb/../early_init.c
-static void early_pch_init(void)
-{
-	u8 reg8;
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
-}
-
-static void setup_sio_gpios(void)
+void mainboard_config_superio(void)
 {
 	const u16 port = SIO_PORT;
 	const u16 runtime_port = 0x180;
@@ -121,13 +108,9 @@
 	outb(0xaa, port);
 }
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	int boot_mode = 0;
-	int cbmem_was_initted;
-
-	struct pei_data pei_data = {
+	struct pei_data pei_data_template = {
 		.pei_version = PEI_VERSION,
 		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -170,86 +153,14 @@
 			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
 		},
 	};
+	*pei_data = pei_data_template;
+}
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
+void mainboard_early_init(int s3resume)
+{
+}
 
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-	setup_pch_gpios(&emeraldlake2_gpio_map);
-	setup_sio_gpios();
-
-	/* Early SuperIO setup */
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk(BIOS_DEBUG, "soft reset detected\n");
-		boot_mode = 1;
-
-		/* System is not happy after keyboard reset... */
-		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
-		outb(0x6, 0xcf9);
-		halt();
-	}
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
-	boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	/* Prepare USB controller early in S3 resume */
-	if (boot_mode == 2)
-		enable_usb_bar();
-
-	post_code(0x3a);
-	pei_data.boot_mode = boot_mode;
-	timestamp_add_now(TS_BEFORE_INITRAM);
-	sdram_initialize(&pei_data);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-	post_code(0x3b);
-	/* Perform some initialization that must run before stage2 */
-	early_pch_init();
-	post_code(0x3c);
-
-	/* This should probably go away. Until now it is required
-	 * and mainboard specific
-	 */
-	rcba_config();
-	post_code(0x3d);
-
-	quick_ram_check();
-	post_code(0x3e);
-
-	cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-	if (boot_mode!=2)
-		save_mrc_data(&pei_data);
-
-	if (boot_mode==2 && !cbmem_was_initted) {
-		/* Failed S3 resume, reset to come up cleanly */
-		outb(0x6, 0xcf9);
-		halt();
-	}
-	northbridge_romstage_finalize(boot_mode==2);
-
-	post_code(0x3f);
-	if (CONFIG_LPC_TPM) {
-		init_tpm(boot_mode == 2);
-	}
+int mainboard_should_reset_usb(int s3resume)
+{
+	return !s3resume;
 }