src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index d3847a5..f570040 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -51,7 +51,7 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1670091..ea60085 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -154,7 +154,7 @@
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -195,7 +195,7 @@
void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -260,8 +260,8 @@
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 9543536..54c3fff 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -156,7 +156,7 @@
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -197,7 +197,7 @@
void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -262,8 +262,8 @@
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
- unsigned ndata, n/*, me_data_len*/;
- unsigned expected;
+ unsigned int ndata, n/*, me_data_len*/;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 475def3..de7fc36 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -87,7 +87,7 @@
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
- unsigned try = IOBP_RETRY;
+ unsigned int try = IOBP_RETRY;
u32 data;
while (try--) {
@@ -147,7 +147,7 @@
#ifndef __SMM__
/* Set bit in function disable register to hide this device */
-static void pch_hide_devfn(unsigned devfn)
+static void pch_hide_devfn(unsigned int devfn)
{
switch (devfn) {
case PCI_DEVFN(20, 0): /* xHCI */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 22b9107..ac976c2 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,7 +66,7 @@
void enable_usb_bar(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void early_thermal_init(void);
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 2c2f9d9..98a4bdb 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,8 +74,8 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 0245f4f..0669b5f 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -124,11 +124,11 @@
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
+ unsigned int bitmask = 1;
+ unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 019009e..eba2d01 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -172,7 +172,7 @@
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 73181cf..a84a0df 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -102,7 +102,7 @@
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
- unsigned databytes;
+ unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@@ -169,7 +169,7 @@
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -178,7 +178,7 @@
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -187,7 +187,7 @@
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -195,21 +195,21 @@
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -367,13 +367,13 @@
uint32_t offset;
} spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
@@ -801,8 +801,8 @@
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to read %x-%x which is out of chip\n",
- (unsigned) addr,
- (unsigned) addr+(unsigned) len);
+ (unsigned int) addr,
+ (unsigned int) addr+(unsigned int) len);
return -1;
}
@@ -872,7 +872,7 @@
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to write 0x%x-0x%x which is out of chip\n",
- (unsigned)addr, (unsigned) (addr+len));
+ (unsigned int)addr, (unsigned int) (addr+len));
return -1;
}
@@ -906,7 +906,7 @@
len -= block_len;
}
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
- (unsigned) (addr - start), start);
+ (unsigned int) (addr - start), start);
return 0;
}
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 48b77699..da0c54b 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -51,7 +51,7 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 1a916f4..6a27fea 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -119,6 +119,6 @@
* Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of GPIO pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index ec66c43..3512f19 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -59,7 +59,7 @@
}
/* Set bit in Function Disable register to hide this device */
-static void soc_hide_devfn(unsigned devfn)
+static void soc_hide_devfn(unsigned int devfn)
{
/* TODO Function Disable. */
}
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index d2f2a0b..f58677b 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -121,7 +121,7 @@
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
- unsigned databytes;
+ unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@@ -199,7 +199,7 @@
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -207,7 +207,7 @@
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -215,7 +215,7 @@
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -223,21 +223,21 @@
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -397,13 +397,13 @@
uint32_t offset;
} spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 9aa3017..50122d8 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -36,7 +36,7 @@
void i82801dx_enable(struct device *dev);
void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
void aseg_smm_lock(void);
#endif
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 6949a30..54ad3c3 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -52,7 +52,7 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 341a98a..132b684 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -137,7 +137,7 @@
(1 << 29) | (1 << 17) | (2 << 2));
}
-static int i82801ix_function_disabled(const unsigned devfn)
+static int i82801ix_function_disabled(const unsigned int devfn)
{
struct device *const dev = pcidev_path_on_root(devfn);
if (!dev) {
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 7c4faf0..906d24e 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -215,7 +215,7 @@
void i82801ix_dmi_poll_vc1(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
#endif
#endif
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index f7d8b87..47254f9 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -34,8 +34,8 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index d2b87d1..adba27c 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -47,7 +47,7 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 28c9f68..7b88218 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -227,7 +227,7 @@
#if ENV_ROMSTAGE
void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
u8 *buf);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index a4f5a01..a24685a 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -34,8 +34,8 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 241584b..bd130c0 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -51,22 +51,22 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-int smbus_write_byte(unsigned device, unsigned address, u8 data)
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
}
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 8d3ae02..f804126 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -155,7 +155,7 @@
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -196,7 +196,7 @@
void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -261,8 +261,8 @@
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 9e5fa24..9ee76f2 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -56,10 +56,10 @@
void enable_usb_bar(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
-int smbus_write_byte(unsigned device, unsigned address, u8 data);
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+int smbus_read_byte(unsigned int device, unsigned int address);
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
#endif
void early_pch_init(void);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 95cac81..d31fd70 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -68,8 +68,8 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index d3847a5..f570040 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -51,7 +51,7 @@
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index bc8d8a1..1919d58 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -127,11 +127,11 @@
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
+ unsigned int bitmask = 1;
+ unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fa6d700..8436243 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -169,7 +169,7 @@
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index b43a1ae..59a8666 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -162,7 +162,7 @@
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -202,7 +202,7 @@
static int mei_send_packet(struct mei_header *mei, void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write */
@@ -306,8 +306,8 @@
{
struct mei_header mei_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index a57bae3..dc7b958 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -197,7 +197,7 @@
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
- unsigned try;
+ unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
u16 status = RCBA16(IOBPS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index be4285b..d83dd17 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -177,7 +177,7 @@
void enable_smbus(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 1eb8e4b..92dd02e 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -168,7 +168,7 @@
static void pch_pcie_device_set_func(int index, int pci_func)
{
struct device *dev;
- unsigned new_devfn;
+ unsigned int new_devfn;
dev = rpc.ports[index];