AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig
index 6e3a4ab..d3d8bec 100644
--- a/src/mainboard/advansus/a785e-i/Kconfig
+++ b/src/mainboard/advansus/a785e-i/Kconfig
@@ -33,10 +33,6 @@
select HAVE_DEBUG_CAR
select SET_FIDVID
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default advansus/a785e-i
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index cf8ec26..737bb1c 100755
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -1,8 +1,6 @@
#romstage-y += reset.c #FIXME romstage have include test_rest.c
-romstage-y += pmio.c
ramstage-y += reset.c
-ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
diff --git a/src/mainboard/advansus/a785e-i/fadt.c b/src/mainboard/advansus/a785e-i/fadt.c
index 53540e7..c9d36f1 100644
--- a/src/mainboard/advansus/a785e-i/fadt.c
+++ b/src/mainboard/advansus/a785e-i/fadt.c
@@ -26,27 +26,14 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-#include "pmio.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of rs780. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
@@ -70,39 +57,39 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
@@ -145,7 +132,7 @@
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
@@ -159,7 +146,7 @@
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -173,21 +160,21 @@
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c
index 2a3f70b..5c21e09 100644
--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c
+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c
@@ -27,6 +27,9 @@
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
@@ -144,4 +147,8 @@
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_sb800 = apicid_base + 0;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index 6340d97..ff2d395 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -25,8 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-//#include <southbridge/amd/sb800/sb800.h>
-#include "pmio.h"
+#include "SBPLATFORM.h"
#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
@@ -39,26 +38,21 @@
/* GPIO6. */
void enable_int_gfx(void)
{
- u8 byte;
-
volatile u8 *gpio_reg;
- pm_iowrite(0xEA, 0x01); /* diable the PCIB */
- /* Disable Gec */
- byte = pm_ioread(0xF6);
- byte |= 1;
- pm_iowrite(0xF6, byte);
- /* make sure the fed80000 is accessible */
- byte = pm_ioread(0x24);
- byte |= 1;
- pm_iowrite(0x24, byte);
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the Acpi MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index dc76b81..72733c6 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -23,8 +23,8 @@
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
-#include "pmio.h"
#include <cpu/amd/amdfam10_sysconf.h>
+#include <SBPLATFORM.h>
extern int bus_isa;
extern u8 bus_rs780[11];
@@ -61,12 +61,8 @@
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
new file mode 100644
index 0000000..11cc504
--- /dev/null
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _A785E_I_CFG_H_
+#define _A785E_I_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
diff --git a/src/mainboard/advansus/a785e-i/pmio.c b/src/mainboard/advansus/a785e-i/pmio.c
deleted file mode 100644
index aa4e61e..0000000
--- a/src/mainboard/advansus/a785e-i/pmio.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
diff --git a/src/mainboard/advansus/a785e-i/pmio.h b/src/mainboard/advansus/a785e-i/pmio.h
deleted file mode 100644
index 78ab6e9..0000000
--- a/src/mainboard/advansus/a785e-i/pmio.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 9e31779..3a33b5f 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -47,7 +47,7 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include <SbEarly.h>
+#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
@@ -82,21 +82,6 @@
outb(0x06, 0x0cf9);
}
-//FIXME copyed from sb800
-#include <pmio.h>
-static void sb800_clk_output_48Mhz(void)
-{
- /* AcpiMMioDecodeEn */
- u8 reg8;
- reg8 = pm_ioread(0x24);
- reg8 |= 1;
- reg8 &= ~(1 << 1);
- pm_iowrite(0x24, reg8);
-
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-}
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -112,7 +97,7 @@
enumerate_ht_chain();
//enable port80 decoding and southbridge poweron init
- sb_poweron_init();
+ sb_Poweron_Init();
}
post_code(0x30);
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 8745125..b494943 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -50,10 +50,6 @@
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/inagua
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index 564d196..955ed80 100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -30,8 +30,7 @@
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
-#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
+#subdirs-$(CONFIG_AMD_SB_CIMX) += ../../../vendorcode/amd/cimx
diff --git a/src/mainboard/amd/inagua/fadt.c b/src/mainboard/amd/inagua/fadt.c
index c31a0e4..c84edfb 100644
--- a/src/mainboard/amd/inagua/fadt.c
+++ b/src/mainboard/amd/inagua/fadt.c
@@ -28,27 +28,14 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
+#include "SBPLATFORM.h"
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@@ -71,38 +58,38 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
@@ -145,7 +132,7 @@
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
@@ -160,7 +147,7 @@
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -175,7 +162,7 @@
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
@@ -183,7 +170,7 @@
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
@@ -191,7 +178,7 @@
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index 43b9013..fedab75 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -24,6 +24,9 @@
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -136,4 +139,8 @@
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 86f08db..e3cd5d0 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -26,6 +26,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
+#include <SBPLATFORM.h>
#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
extern u8 bus_sb800[2];
@@ -116,11 +117,8 @@
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
new file mode 100644
index 0000000..d37c7e6
--- /dev/null
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _INAGUA_CFG_H_
+#define _INAGUA_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
diff --git a/src/mainboard/amd/inagua/pmio.c b/src/mainboard/amd/inagua/pmio.c
deleted file mode 100644
index baded54..0000000
--- a/src/mainboard/amd/inagua/pmio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
diff --git a/src/mainboard/amd/inagua/pmio.h b/src/mainboard/amd/inagua/pmio.h
deleted file mode 100644
index 207fdc2..0000000
--- a/src/mainboard/amd/inagua/pmio.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 57953bc..c4e8b15 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -33,7 +33,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
#include <arch/cpu.h>
@@ -52,7 +52,7 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
kbc1100_early_init(CONFIG_SIO_PORT);
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index c4eac67..f900584 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -47,10 +47,6 @@
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/persimmon
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index de3564a..6a19bb6 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -37,6 +37,5 @@
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/persimmon/fadt.c b/src/mainboard/amd/persimmon/fadt.c
index 0b37885..020d011 100644
--- a/src/mainboard/amd/persimmon/fadt.c
+++ b/src/mainboard/amd/persimmon/fadt.c
@@ -28,27 +28,14 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
+#include "SBPLATFORM.h"
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@@ -71,38 +58,38 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
@@ -145,7 +132,7 @@
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
@@ -160,7 +147,7 @@
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -175,7 +162,7 @@
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
@@ -183,7 +170,7 @@
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
@@ -191,7 +178,7 @@
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index cc7fb5d..355c27f 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -24,6 +24,9 @@
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -127,4 +130,8 @@
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 9c27c0e..a5aa79e 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -24,6 +24,7 @@
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
+#include <SBPLATFORM.h>
extern u8 bus_sb800[2];
@@ -64,11 +65,8 @@
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
new file mode 100644
index 0000000..c6d2bd5
--- /dev/null
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PERSIMMON_CFG_H_
+#define _PERSIMMON_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
diff --git a/src/mainboard/amd/persimmon/pmio.c b/src/mainboard/amd/persimmon/pmio.c
deleted file mode 100644
index baded54..0000000
--- a/src/mainboard/amd/persimmon/pmio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
diff --git a/src/mainboard/amd/persimmon/pmio.h b/src/mainboard/amd/persimmon/pmio.h
deleted file mode 100644
index 207fdc2..0000000
--- a/src/mainboard/amd/persimmon/pmio.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index dfc2b6a..6067803 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -35,7 +35,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
@@ -57,7 +57,7 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index ff55e24..bd6c633 100755
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -525,7 +525,6 @@
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
- UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
@@ -598,14 +597,14 @@
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
if (ResetInfo->ResetControl == DeassertSlotReset) {
- if (ResetInfo->ResetId & BIT2+BIT3) { //de-assert
+ if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
if (Data8 & BIT7) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
while (!(Data8 & BIT7)) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
- }
+ }
// GPIO44: PE_GPIO0 MXM Reset
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 |= BIT6 ;
diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
index 57d8c05..e4bde59 100755
--- a/src/mainboard/amd/torpedo/Kconfig
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -50,10 +50,6 @@
bool
default y
-config AMD_CIMX_SB900
- bool
- default y
-
config MAINBOARD_DIR
string
default amd/torpedo
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
index 1a7dc95..986d90d7 100755
--- a/src/mainboard/amd/torpedo/Makefile.inc
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -36,7 +36,6 @@
romstage-y += dimmSpd.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
-romstage-y += cfg.c
romstage-y += gpio.c
ramstage-y += buildOpts.c
@@ -44,7 +43,6 @@
ramstage-y += dimmSpd.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
-ramstage-y += cfg.c
ramstage-y += reset.c
ramstage-y += pmio.c
diff --git a/src/mainboard/amd/torpedo/cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
old mode 100755
new mode 100644
similarity index 99%
rename from src/mainboard/amd/torpedo/cfg.h
rename to src/mainboard/amd/torpedo/platform_cfg.h
index 6565d6c..532d83f
--- a/src/mainboard/amd/torpedo/cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -39,7 +39,6 @@
#define BIOS_SIZE_4M 3
#define BIOS_SIZE_8M 7
-#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
@@ -49,7 +48,6 @@
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#define BIOS_SIZE BIOS_SIZE_8M
#endif
-#endif
/**
* @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index e6153c0..c60f6df 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -47,10 +47,6 @@
bool
default y
-config AMD_CIMX_SB800
- bool
- default y
-
config MAINBOARD_DIR
string
default asrock/e350m1
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index 0f17032..22d8373 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -30,6 +30,5 @@
ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
-ramstage-y += pmio.c
subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/fadt.c b/src/mainboard/asrock/e350m1/fadt.c
index 0b37885..020d011 100644
--- a/src/mainboard/asrock/e350m1/fadt.c
+++ b/src/mainboard/asrock/e350m1/fadt.c
@@ -28,27 +28,14 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
+#include "SBPLATFORM.h"
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
+ u16 val = 0;
acpi_header_t *header = &(fadt->header);
- pm_base &= 0xFFFF;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+ printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
@@ -71,38 +58,38 @@
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
- pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
- pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
- pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
- pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
- pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
- pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
- pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+ val = PM1_EVT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+ val = PM1_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+ val = PM1_TMR_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+ val = GPE0_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+ val = CPU_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+ val = 0;
+ WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+ val = ACPI_PMA_CNT_BLK_ADDRESS;
+ WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
- pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
- pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+ /* AcpiDecodeEnable, When set, SB uses the contents of the
+ * PM registers at index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ val = BIT0 | BIT1 | BIT2 | BIT4;
+ WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
- pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
- pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
- pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
- outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
+ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+ fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+ fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
@@ -145,7 +132,7 @@
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
@@ -160,7 +147,7 @@
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -175,7 +162,7 @@
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
@@ -183,7 +170,7 @@
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
@@ -191,7 +178,7 @@
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index cc7fb5d..4386717 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -24,6 +24,9 @@
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include "sb_cimx.h"
+#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -127,4 +130,8 @@
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_Late_Post();
+#endif
}
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index e286e6f..05c2275 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -24,6 +24,7 @@
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
+#include <SBPLATFORM.h>
extern u8 bus_sb800[2];
@@ -64,11 +65,8 @@
u32 dword;
u8 byte;
- dword = 0;
- dword = pm_ioread(0x34) & 0xF0;
- dword |= (pm_ioread(0x35) & 0xFF) << 8;
- dword |= (pm_ioread(0x36) & 0xFF) << 16;
- dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
new file mode 100644
index 0000000..6e0faea
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _E350M1_CFG_H_
+#define _E350M1_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+#endif
diff --git a/src/mainboard/asrock/e350m1/pmio.c b/src/mainboard/asrock/e350m1/pmio.c
deleted file mode 100644
index baded54..0000000
--- a/src/mainboard/asrock/e350m1/pmio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <arch/io.h> /*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
- outb(reg, port_base);
- outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
- return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
- pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
- return pmio_read_index(PM2_INDEX, reg);
-}
-
diff --git a/src/mainboard/asrock/e350m1/pmio.h b/src/mainboard/asrock/e350m1/pmio.h
deleted file mode 100644
index 207fdc2..0000000
--- a/src/mainboard/asrock/e350m1/pmio.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX 0xCD6
-#define PM_DATA 0xCD7
-#define PM2_INDEX 0xCD0
-#define PM2_DATA 0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 38790cd..133aca7 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -35,7 +35,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
@@ -57,7 +57,7 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
- sb_poweron_init();
+ sb_Poweron_Init();
post_code(0x31);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index e38500d..80b9ca6 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -33,6 +33,9 @@
#include "chip.h"
#include "northbridge.h"
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
//#define FX_DEVS NODE_NUMS
@@ -747,6 +750,12 @@
static void domain_enable_resources(device_t dev)
{
u32 val;
+
+#if CONFIG_AMD_SB_CIMX
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+#endif
+
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
val = agesawrapper_amdinitmid ();
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index c647474..89bd673 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -47,6 +47,9 @@
#endif
#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
struct amdfam10_sysconf_t sysconf;
@@ -1445,6 +1448,10 @@
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
+#if CONFIG_AMD_SB_CIMX
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+#endif
}
static void cpu_bus_noop(device_t dev)
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 6a9a7c1..7ec61f4 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -12,6 +12,6 @@
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
-subdirs-$(CONFIG_AMD_CIMX_SB900) += cimx
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
index e7e13c1..8f12b90 100644
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -17,5 +17,9 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+config AMD_SB_CIMX
+ bool
+ default n
+
source src/southbridge/amd/cimx/sb800/Kconfig
source src/southbridge/amd/cimx/sb900/Kconfig
diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
index 6f2d5f1..6ad81c4 100644
--- a/src/southbridge/amd/cimx/sb800/Amd.h
+++ b/src/southbridge/amd/cimx/sb800/Amd.h
@@ -156,7 +156,7 @@
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
+typedef struct _CPUID_DATA {
IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index dc1400f..b5f9325 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -19,7 +19,9 @@
config SOUTHBRIDGE_AMD_CIMX_SB800
bool
+ default n
select IOAPIC
+ select AMD_SB_CIMX
if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index ca64494..acc5fdf 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -17,7 +17,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-subdirs-$(CONFIG_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800
# SB800 Platform Files
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 93e1c31..89b4dc3 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -57,6 +57,7 @@
#endif
#define FIXUP_PTR(ptr) ptr
+#include <console/console.h>
#include "AmdSbLib.h"
#include "Amd.h"
#include "SB800.h"
@@ -65,7 +66,8 @@
#include "SBDEF.h"
#include "AMDSBLIB.h"
#include "SBSUBFUN.h"
-#include "OEM.h"
+#include "platform_cfg.h" /* mainboard specific configuration */
+#include "OEM.h" /* platform default configuration */
#include "AMD.h"
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 0a09e11..57ff718 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -31,8 +31,10 @@
void sb800_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
+ printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n");
return;
}
+ printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n");
//memset(sb_config, 0, sizeof(AMDSBCFG));
/* header */
@@ -73,7 +75,7 @@
sb_config->HpetTimer = HPET_TIMER;
/* USB */
- sb_config->USBMODE.UsbModeReg = USB_CINFIG;
+ sb_config->USBMODE.UsbModeReg = USB_CONFIG;
sb_config->SbUsbPll = 0;
/* SATA */
@@ -99,25 +101,28 @@
sb_config->GppFunctionEnable = GPP_CONTROLLER;
sb_config->GppLinkConfig = GPP_CFGMODE;
//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
- //sb_config->NbSbGen2 = TRUE;
- //sb_config->GppGen2 = TRUE;
+ sb_config->NbSbGen2 = NB_SB_GEN2;
+ sb_config->GppGen2 = SB_GPP_GEN2;
//cimx BTS fix
sb_config->GppMemWrImprove = TRUE;
sb_config->SbPcieOrderRule = TRUE;
sb_config->AlinkPhyPllPowerDown = TRUE;
sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
- sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong
- sb_config->GecConfig = 0; //ENABLE GEC controller
+ sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06
+ sb_config->GecConfig = GEC_CONFIG;
#ifndef __PRE_RAM__
/* ramstage cimx config here */
if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
}
-
- //sb_config->
#endif //!__PRE_RAM__
+ printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h
index 05db9ab..e14283f 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.h
+++ b/src/southbridge/amd/cimx/sb800/cfg.h
@@ -23,202 +23,6 @@
#include <stdint.h>
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M 0
-#define BIOS_SIZE_2M 1
-#define BIOS_SIZE_4M 3
-#define BIOS_SIZE_8M 7
-
-/* In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
- #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
- #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
- #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
- #define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- * 0 - Disable Spread Spectrum function
- * 1 - Enable Spread Spectrum function
- */
-#define SPREAD_SPECTRUM 0
-
-/**
- * @def SB_HPET_TIMER
- * @breif
- * 0 - Disable hpet
- * 1 - Enable hpet
- */
-#define HPET_TIMER 1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- * 0 - Disable
- * 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG 0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @breif bit[0-4] used for PCI Slots Clock Control,
- * 0 - disable
- * 1 - enable
- * PCI SLOT 0 define at BIT0
- * PCI SLOT 1 define at BIT1
- * PCI SLOT 2 define at BIT2
- * PCI SLOT 3 define at BIT3
- * PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL 0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @breif INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
- #define SATA_CONTROLLER CIMX_OPTION_ENABLED
-#endif
-
-/**
- * @def SATA_MODE
- * @breif INCHIP Sata Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
- #define SATA_MODE NATIVE_IDE_MODE
-#endif
-
-/**
- * @breif INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE 0
-#define IDE_NATIVE_MODE 1
-
-/**
- * @def SATA_IDE_MODE
- * @breif INCHIP Sata IDE Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
- #define SATA_IDE_MODE IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- * PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK 0x00
-#define INTERNAL_CLOCK 0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED 1
-
-
-/**
- * @def AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO 0
-#define AZALIA_DISABLE 1
-#define AZALIA_ENABLE 2
-
-/**
- * @breif INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
- #define AZALIA_CONTROLLER AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- * 0 - disable
- * 1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
- #define AZALIA_PIN_CONFIG 1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- * SDIN0 is define at BIT0 & BIT1
- * 00 - GPIO PIN
- * 01 - Reserved
- * 10 - As a Azalia SDIN pin
- * SDIN1 is define at BIT2 & BIT3
- * SDIN2 is define at BIT4 & BIT5
- * SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
- //#define AZALIA_SDIN_PIN 0xAA
- #define AZALIA_SDIN_PIN 0x2A
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
- #define GPP_CONTROLLER CIMX_OPTION_ENABLED
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- * GPP_CFGMODE_X4000
- * GPP_CFGMODE_X2200
- * GPP_CFGMODE_X2110
- * GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
- #define GPP_CFGMODE GPP_CFGMODE_X1111
-#endif
-
-
/**
* @brief South Bridge CIMx configuration
*
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 40a18cc..9d49a52 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -24,10 +24,11 @@
#include <arch/io.h> /* inl, outl */
#include <arch/romcc_io.h> /* device_t */
#include "SBPLATFORM.h"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
+#if CONFIG_RAMINIT_SYSINFO == 1
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
@@ -37,20 +38,23 @@
{
device_t dev;
+ printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
//dev = PCI_DEV(bus, 0x14, 0);
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
bus);
+ printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__);
return (dev >> 15) & 0x1f;
}
+#endif
/**
* @brief South Bridge CIMx romstage entry,
* wrapper of sbPowerOnInit entry point.
*/
-void sb_poweron_init(void)
+void sb_Poweron_Init(void)
{
AMDSBCFG sb_early_cfg;
@@ -62,3 +66,17 @@
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbPowerOnInit(&sb_early_cfg);
}
+
+/**
+ * CIMX not set the clock to 48Mhz until sbBeforePciInit,
+ * coreboot may need to set this even more earlier
+ */
+void sb800_clk_output_48Mhz(void)
+{
+ /* AcpiMMioDecodeEn */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
+
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+}
+
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b16bc50..b581212 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -28,18 +28,14 @@
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
+#include "sb_cimx.h" /* AMD CIMX wrapper entries */
/*implement in mainboard.c*/
-//void set_pcie_assert(void);
-//void set_pcie_deassert(void);
void set_pcie_reset(void);
void set_pcie_dereset(void);
-#ifndef _RAMSTAGE_
-#define _RAMSTAGE_
-#endif
static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
static AMDSBCFG *sb_config = &sb_late_cfg;
@@ -57,15 +53,13 @@
u32 sb800_callout_entry(u32 func, u32 data, void* config)
{
u32 ret = 0;
-
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
switch (func) {
case CB_SBGPP_RESET_ASSERT:
- //set_pcie_assert();
set_pcie_reset();
break;
case CB_SBGPP_RESET_DEASSERT:
- //set_pcie_deassert();
set_pcie_dereset();
break;
@@ -76,32 +70,20 @@
break;
}
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
return ret;
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = pci_dev_set_subsystem,
};
-static void lpc_enable_resources(device_t dev)
-{
-
- pci_dev_enable_resources(dev);
- //lpc_enable_childrens_resources(dev);
-}
-
-static void lpc_init(device_t dev)
-{
- /* SB Configure HPET base and enable bit */
- hpetInit(sb_config, &(sb_config->BuildParameters));
-}
-
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
- .enable_resources = lpc_enable_resources,
- .init = lpc_init,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
.scan_bus = scan_static_bus,
.ops_pci = &lops_pci,
};
@@ -112,26 +94,11 @@
.device = PCI_DEVICE_ID_ATI_SB800_LPC,
};
-
-static void sata_enable_resources(struct device *dev)
-{
- sataInitAfterPciEnum(sb_config);
- pci_dev_enable_resources(dev);
-}
-
-static void sata_init(struct device *dev)
-{
- sb_config->StdHeader.Func = SB_MID_POST_INIT;
- AmdSbDispatcher(sb_config); //sataInitMidPost only
- commonInitLateBoot(sb_config);
- sataInitLatePost(sb_config);
-}
-
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
- .init = sata_init,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
@@ -142,13 +109,14 @@
.device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
};
-#if CONFIG_USBDEBUG
+#if CONFIG_USBDEBUG == 1
static void usb_set_resources(struct device *dev)
{
struct resource *res;
u32 base;
u32 old_debug;
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
old_debug = get_ehci_debug();
set_ehci_debug(0);
@@ -161,15 +129,10 @@
base = res->base;
set_ehci_base(base);
report_resource_stored(dev, res, "");
+ printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
}
#endif
-static void usb_init(struct device *dev)
-{
- usbInitAfterPciInit(sb_config);
- commonInitLateBoot(sb_config);
-}
-
static struct device_operations usb_ops = {
.read_resources = pci_dev_read_resources,
#if CONFIG_USBDEBUG
@@ -178,7 +141,7 @@
.set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_dev_enable_resources,
- .init = usb_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
@@ -205,16 +168,11 @@
};
-static void azalia_init(struct device *dev)
-{
- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
-}
-
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = azalia_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
@@ -226,18 +184,11 @@
};
-static void gec_init(struct device *dev)
-{
- gecInitAfterPciEnum(sb_config);
- gecInitLatePost(sb_config);
- printk(BIOS_DEBUG, "gec hda enabled\n");
-}
-
static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = gec_init,
+ .init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
@@ -264,10 +215,6 @@
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
}
-static void pcie_init(device_t dev)
-{
- sbPcieGppLateInit(sb_config);
-}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
@@ -290,7 +237,7 @@
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
+ .init = 0,
.scan_bus = pci_scan_bridge,
.enable = 0,
.reset_bus = pci_bus_reset,
@@ -327,6 +274,34 @@
/**
+ * South Bridge CIMx ramstage entry point wrapper.
+ */
+void sb_Before_Pci_Init(void)
+{
+ sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_After_Pci_Init(void)
+{
+ sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_Mid_Post_Init(void)
+{
+ sb_config->StdHeader.Func = SB_MID_POST_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_Late_Post(void)
+{
+ sb_config->StdHeader.Func = SB_LATE_POST_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+
+/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb800_enable(device_t dev)
@@ -334,15 +309,13 @@
struct southbridge_amd_cimx_sb800_config *sb_chip =
(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
- sb800_cimx_config(sb_config);
printk(BIOS_DEBUG, "sb800_enable() ");
- /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
- commonInitEarlyBoot(sb_config);
- commonInitEarlyPost(sb_config);
-
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
+ /* the first sb800 device */
+ sb800_cimx_config(sb_config);
+
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
@@ -352,39 +325,21 @@
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
}
-
- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
- break;
-
- case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
- case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
- case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
- case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
- case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
- case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
- case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
- {
- u32 ioapic_base;
-
- printk(BIOS_INFO, "sm_init().\n");
- ioapic_base = IO_APIC_ADDR;
- clear_ioapic(ioapic_base);
- /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
- #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
- /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
- #elif (CONFIG_APIC_ID_OFFSET > 0)
- /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
- setup_ioapic(ioapic_base, 0);
- #else
- #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
- #endif
- }
-
+ printk(BIOS_INFO, "sm_init().\n");
+ clear_ioapic(IO_APIC_ADDR);
+ /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+#elif (CONFIG_APIC_ID_OFFSET > 0)
+ /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+ setup_ioapic(IO_APIC_ADDR, 0);
+#else
+#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+#endif
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
@@ -393,7 +348,6 @@
} else {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
}
- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
@@ -406,7 +360,6 @@
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
break;
@@ -424,34 +377,55 @@
sb_config->GecConfig = 1;
printk(BIOS_DEBUG, "gec disabled\n");
}
- gecInitBeforePciEnum(sb_config); // Init GEC
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
{
- device_t device;
- for (device = dev; device; device = device->next) {
- if (dev->path.type != DEVICE_PATH_PCI) continue;
- if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
- sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
- }
+ device_t device;
+ for (device = dev; device; device = device->next) {
+ if (dev->path.type != DEVICE_PATH_PCI) continue;
+ if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
+ sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+ }
- /*
- * GPP_CFGMODE_X4000: PortA Lanes[3:0]
- * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
- * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
- * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
- */
- sb_config->GppLinkConfig = sb_chip->gpp_configuration;
- sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
- AmdSbDispatcher(sb_config);
- break;
+ /*
+ * GPP_CFGMODE_X4000: PortA Lanes[3:0]
+ * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
+ * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+ sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
+ break;
+
+ case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+ sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
+ break;
+ case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+ sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
+ break;
+ case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+ sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
+ break;
+ case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+ sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
+ break;
+ case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+ sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
+ break;
+ case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
+ sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
+ break;
+ case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
+ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
+
+ /* the last sb800 device */
+ sb_Before_Pci_Init();
+ break;
default:
break;
}
-
}
struct chip_operations southbridge_amd_cimx_sb800_ops = {
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index 39762a9..bc643b5 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
#include <device/pci.h>
#include "lpc.h"
@@ -25,6 +26,7 @@
{
struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n");
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
@@ -49,18 +51,20 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev);
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n");
}
void lpc_set_resources(struct device *dev)
{
struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
-
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n");
}
/**
@@ -76,6 +80,7 @@
int var_num = 0;
u16 reg_var[3];
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
reg = pci_read_config32(dev, 0x44);
reg_x = pci_read_config32(dev, 0x48);
@@ -170,4 +175,5 @@
//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
break;
}
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb800/SbEarly.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
similarity index 70%
rename from src/southbridge/amd/cimx/sb800/SbEarly.h
rename to src/southbridge/amd/cimx/sb800/sb_cimx.h
index 2dd0e6d..42a7ba9 100644
--- a/src/southbridge/amd/cimx/sb800/SbEarly.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -18,20 +18,30 @@
*/
-#ifndef _CIMX_SB_EARLY_H_
-#define _CIMX_SB_EARLY_H_
+#ifndef _CIMX_H_
+#define _CIMX_H_
/**
+ * AMD South Bridge CIMx entry point wrapper
+ */
+void sb_Poweron_Init(void);
+void sb_Before_Pci_Init(void);
+void sb_After_Pci_Init(void);
+void sb_Mid_Post_Init(void);
+void sb_Late_Post(void);
+
+/**
+ * CIMX not set the clock to 48Mhz until sbBeforePciInit,
+ * coreboot may need to set this even more earlier
+ */
+void sb800_clk_output_48Mhz(void);
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
* @brief Get SouthBridge device number, called by finalize_node_setup()
* @param[in] bus target bus number
* @return southbridge device number
*/
u32 get_sbdn(u32 bus);
-
-/**
- * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
- */
-void sb_poweron_init(void);
-//void sb_before_pci_init(void);
-
+#endif
#endif
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 4b13fdb..4dc76ba 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include "smbus.h"
+#include <console/console.h> /* printk */
static inline void smbus_delay(void)
{
@@ -71,9 +72,11 @@
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n");
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
@@ -90,6 +93,7 @@
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTCMD);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n");
return byte;
}
@@ -98,9 +102,11 @@
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n");
/* set the command... */
outb(val, smbus_io_base + SMBHSTCMD);
@@ -117,6 +123,7 @@
return -3; /* timeout or error */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n");
return 0;
}
@@ -125,9 +132,11 @@
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n");
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -147,6 +156,7 @@
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTDAT0);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n");
return byte;
}
@@ -155,9 +165,11 @@
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
return -2; /* not ready */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n");
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -177,6 +189,7 @@
return -3; /* timeout or error */
}
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n");
return 0;
}
@@ -184,6 +197,7 @@
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n");
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
tmp = inl(AB_DATA);
/* rpr 4.2
@@ -199,12 +213,14 @@
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n");
}
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n");
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
tmp = inl(AB_DATA);
/* rpr 4.2
@@ -220,6 +236,7 @@
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n");
}
/* space = 0: AX_INDXC, AX_DATAC
@@ -229,6 +246,7 @@
{
u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n");
/* read axindc to tmp */
outl(space << 29 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
@@ -247,5 +265,6 @@
outl(space << 29 | space << 3 | 0x34, AB_INDX);
outl(tmp, AB_DATA);
outl(0, AB_INDX);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 46f635e..253d73f 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -19,7 +19,9 @@
config SOUTHBRIDGE_AMD_CIMX_SB900
bool
+ default n
select IOAPIC
+ select AMD_SB_CIMX
if SOUTHBRIDGE_AMD_CIMX_SB900
config SATA_CONTROLLER_MODE
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc
index 17618f9..4a8da05 100755
--- a/src/southbridge/amd/cimx/sb900/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb900/Makefile.inc
@@ -17,15 +17,17 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
# SB900 Platform Files
+romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c
-ramstage-y += late.c
+ramstage-y += cfg.c
ramstage-y += early.c
+ramstage-y += late.c
driver-y += smbus.c
driver-y += lpc.c
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 0a2e65a..3fb45de 100755
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -57,6 +57,7 @@
#endif
#define FIXUP_PTR(ptr) ptr
+#include <console/console.h>
#include "AmdSbLib.h"
#include "Amd.h"
#include "Hudson-2.h"
@@ -65,7 +66,8 @@
#include "SbDef.h"
#include "AmdSbLib.h"
#include "SbSubFun.h"
-#include "Oem.h"
+#include "platform_cfg.h" /* mainboard specific configuration */
+#include "Oem.h" /* platform default configuration */
#include "AMD.h"
#include "SbBiosRamUsage.h"
#include "EcFan.h"
diff --git a/src/mainboard/amd/torpedo/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
old mode 100755
new mode 100644
similarity index 99%
rename from src/mainboard/amd/torpedo/cfg.c
rename to src/southbridge/amd/cimx/sb900/cfg.c
index 809b7a3..19d9ae2
--- a/src/mainboard/amd/torpedo/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -20,8 +20,7 @@
#include <string.h>
#include "SbPlatform.h"
-#include "cfg.h"
-#include <console/console.h> /* printk */
+#include "platform_cfg.h"
/**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e09eb29..bd4fd4f 100755
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -25,7 +25,6 @@
#include <arch/romcc_io.h> /* device_t */
#include "SbPlatform.h"
#include "SbEarly.h"
-#include "cfg.h" /*sb900_cimx_config*/
#include <console/console.h>
#include <console/loglevel.h>
#include "smbus.h"
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index eb17a33..71c65e3 100755
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -25,7 +25,6 @@
#include <console/console.h> /* printk */
#include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */
-#include "cfg.h" /* sb900 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
index 83722d8..6c92227 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
+++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
@@ -113,5 +113,6 @@
void WriteIo8(IN unsigned short Address, IN unsigned char Data);
void WriteIo16(IN unsigned short Address, IN unsigned short Data);
void WriteIo32(IN unsigned short Address, IN unsigned int Data);
-void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value);
+void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value);
unsigned char ReadNumberOfCpuCores(void);
diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h
index 6ca4271..9abea30 100644
--- a/src/vendorcode/amd/cimx/sb800/OEM.h
+++ b/src/vendorcode/amd/cimx/sb800/OEM.h
@@ -30,7 +30,9 @@
*
*/
-#define BIOS_SIZE 0x04 //04 - 1MB
+#ifndef BIOS_SIZE
+ #define BIOS_SIZE 0x04 //04 - 1MB
+#endif
#define LEGACY_FREE 0x00
//#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
diff --git a/src/vendorcode/amd/cimx/sb900/Oem.h b/src/vendorcode/amd/cimx/sb900/Oem.h
index edda541..14bc530 100755
--- a/src/vendorcode/amd/cimx/sb900/Oem.h
+++ b/src/vendorcode/amd/cimx/sb900/Oem.h
@@ -27,7 +27,9 @@
;
;*********************************************************************************/
-#define BIOS_SIZE 0x04 //04 - 1MB
+#ifndef BIOS_SIZE
+ #define BIOS_SIZE 0x04 //04 - 1MB
+#endif
#define LEGACY_FREE 0x00
#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01