soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntax
Replace `Add (a, b)` with `a + b`.
Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 3e4f8e2..31efcb9 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -159,7 +159,7 @@
{
Store (LPFW, LMIN)
Store (0x00100000, LLEN)
- Subtract (Add (LMIN, LLEN), One, LMAX)
+ Subtract (LMIN + LLEN, One, LMAX)
}
Else
{
@@ -238,7 +238,7 @@
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
- Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
+ Store (CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0, RBAS)
Return (^RBUF)
}
}
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 3b33a79..0a4dbd1 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -157,7 +157,7 @@
If (LAnd (LPFW != Zero, LPEN == One))
{
Store (LPFW, LMIN)
- Store (Add (LMIN, 0x001FFFFF), LMAX)
+ Store (LMIN + 0x001FFFFF, LMAX)
Store (0x00200000, LLEN)
}
Else
@@ -237,7 +237,7 @@
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
- Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
+ Store (CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xD0, RBAS)
Return (^RBUF)
}
}