soc/intel/denverton_ns: Allow using FSP repo
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with Denverton
systems.
Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 9a61127..a74250b 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -79,6 +79,15 @@
help
The memory location of the Intel FSP-S binary for this platform.
+config FSP_HEADER_PATH
+ string
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"
+
+config FSP_FD_PATH
+ string
+ depends on FSP_USE_REPO
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd"
+
# CAR memory layout on DENVERTON_NS hardware:
## CAR base address - 0xfef00000
## CAR size 1MB - 0x100 (0xfff00)
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index 4050f61..7529892 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -86,10 +86,8 @@
verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns
##Set FSP binary blobs memory location
-
$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip
$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip