diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 76e75c8..ad2586c 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -57,15 +57,15 @@
 	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
 
 	/* Global SMI Lock */
-	pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+	pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
 
 	/* GEN_PMCON Lock */
-	pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+	pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
 
 	/* R/WO registers */
 	RCBA32(0x21a4) = RCBA32(0x21a4);
-	pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
-		    pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
 
 	/* Indicate finalize step with post code */
 	outb(POST_OS_BOOT, 0x80);