tree 597063b76d3b640d5d71e40d060a6cd954342dce
parent ebba6da073e51569bd962e86bf8162e7b4da9321
author Angel Pons <th3fanbus@gmail.com> 1631104207 +0200
committer Matt DeVillier <matt.devillier@gmail.com> 1713231936 +0000

lynxpoint/broadwell: Correct L1 exit latency with ASPM

Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).

Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>