commit | ccc27d2ccad2e016262923ee241b1569a6085118 | [log] [tgz] |
---|---|---|
author | Dmitry Ponamorev <dponamorev@gmail.com> | Wed Sep 15 03:19:15 2021 -0700 |
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Wed Dec 15 12:10:02 2021 +0000 |
tree | 8e60c02d1e2be2c56a1de117a6049cea9d16eb6e | |
parent | add2e930505be3470092774f595cdb8b3ff61ef2 [diff] |
soc/intel/baytrail,denverton_ns: Call setup_lapic() A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Similar change was done for soc/intel/braswell in commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1. Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.