diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h
index 7baba30..e211d4c 100644
--- a/src/northbridge/amd/amdht/h3gtopo.h
+++ b/src/northbridge/amd/amdht/h3gtopo.h
@@ -324,7 +324,7 @@
 	0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF	// Node7
 };
 
-static const u8 * const amd_topo_list[] = {
+static const u8 *const amd_topo_list[] = {
 	amdHtTopologySingleNode,
 	amdHtTopologyDualNode,
 	amdHtTopologyThreeLine,
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index f4e8337..08ecb4d 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -65,7 +65,7 @@
 
 typedef struct {
 	uint32_t code;
-	const char * string;
+	const char *string;
 } event_string_decode_t;
 
 static const event_string_decode_t event_string_decodes[] = {
@@ -90,7 +90,8 @@
 	{ HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" }
 };
 
-static const char * event_string_decode(uint32_t event) {
+static const char *event_string_decode(uint32_t event)
+{
 	uint32_t i;
 	for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++)
 		if (event_string_decodes[i].code == event)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index a02f49b..3cda13f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -1055,13 +1055,13 @@
 void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 dct);
 uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
 void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
 		struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable);
-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,
+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,
 			uint8_t dct, uint8_t dimm, uint32_t index_reg);
-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,
+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,
 			uint8_t dct, uint8_t dimm, uint32_t index_reg);
 void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat);
@@ -1133,7 +1133,7 @@
 void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
 	struct DCTStatStruc *pDCTstat, uint8_t dct,
 	uint8_t Receiver, uint8_t lane, uint8_t stop_on_error);
-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
 
 uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
 			struct DCTStatStruc *pDCTstat, uint8_t dct);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 9b74817..0429993 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -317,7 +317,7 @@
 	pDCTstat->DQSDelay = (u8)DQSDelay;
 }
 
-static void read_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint32_t dword;
 	uint32_t mask;
@@ -346,7 +346,7 @@
 	delay[8] = dword & mask;
 }
 
-static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint32_t dword;
 	uint32_t mask;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 7c3781f..bae2e89 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -255,7 +255,7 @@
 	return seed;
 }
 
-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t dword;
@@ -282,7 +282,7 @@
 }
 
 #ifdef UNUSED_CODE
-static void write_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t dword;
@@ -314,7 +314,7 @@
 }
 #endif
 
-static void write_write_data_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t dword;
@@ -353,7 +353,7 @@
 	}
 }
 
-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t mask;
@@ -387,7 +387,7 @@
 	}
 }
 
-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t mask;
@@ -424,7 +424,7 @@
 	}
 }
 
-static void read_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t dword;
@@ -456,7 +456,7 @@
 	}
 }
 
-static void write_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t lane;
 	uint32_t dword;
@@ -494,7 +494,7 @@
 	}
 }
 
-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t shift;
 	uint32_t dword;
@@ -528,7 +528,7 @@
 	delay[8] = (dword & mask) >> shift;
 }
 
-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
 {
 	uint8_t shift;
 	uint32_t dword;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 84e26ea..4c33a2f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -194,11 +194,11 @@
 	return ret;
 }
 
-static struct amd_s3_persistent_data * map_s3nv_in_nvram(void)
+static struct amd_s3_persistent_data *map_s3nv_in_nvram(void)
 {
 	ssize_t s3nv_offset;
 	ssize_t s3nv_file_offset;
-	void * s3nv_cbfs_file_ptr;
+	void *s3nv_cbfs_file_ptr;
 	struct amd_s3_persistent_data *persistent_data;
 
 	/* Obtain CBFS file offset */
@@ -269,7 +269,7 @@
 	return pci_read_config32(dev, reg);
 }
 
-static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored)
+static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored)
 {
 	uint8_t node;
 	uint8_t dimm;
@@ -303,7 +303,7 @@
 	}
 }
 
-void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
+void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data)
 {
 	uint8_t i;
 	uint8_t j;
@@ -326,7 +326,7 @@
 		persistent_data->node[node].node_present = 1;
 
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 
 			/* Stage 1 */
 			data->f2x110 = pci_read_config32(dev_fn2, 0x110);
@@ -594,7 +594,7 @@
 	wrmsr(index, msr);
 }
 
-void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only)
+void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)
 {
 	uint8_t i;
 	uint8_t j;
@@ -608,7 +608,7 @@
 		/* Only restore the Receiver Enable and DQS training registers */
 		for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 			for (channel = 0; channel < 2; channel++) {
-				struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+				struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 				if (!persistent_data->node[node].node_present)
 					continue;
 
@@ -652,7 +652,7 @@
 	/* Stage 1 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -663,7 +663,7 @@
 	/* Stage 2 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -719,7 +719,7 @@
 	/* Stage 3 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -758,7 +758,7 @@
 	if (is_fam15h()) {
 		for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 			for (channel = 0; channel < 2; channel++) {
-				struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+				struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 				if (!persistent_data->node[node].node_present)
 					continue;
 
@@ -823,7 +823,7 @@
 	/* Stage 4 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -868,7 +868,7 @@
 	/* Stage 5 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -909,7 +909,7 @@
 	/* Stage 6 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -926,7 +926,7 @@
 	if (is_fam15h()) {
 		for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 			for (channel = 0; channel < 2; channel++) {
-				struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+				struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 				if (!persistent_data->node[node].node_present)
 					continue;
 
@@ -964,7 +964,7 @@
 	/* Stage 7 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -983,7 +983,7 @@
 	/* Stage 8 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -1010,7 +1010,7 @@
 	/* Stage 9 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -1034,7 +1034,7 @@
 	/* Stage 10 */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
@@ -1066,7 +1066,7 @@
 	if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
 		for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 			for (channel = 0; channel < 2; channel++) {
-				struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+				struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 				if (!persistent_data->node[node].node_present)
 					continue;
 
@@ -1081,7 +1081,7 @@
 	/* Other */
 	for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
 		for (channel = 0; channel < 2; channel++) {
-			struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+			struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
 			if (!persistent_data->node[node].node_present)
 				continue;
 
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index a66917b..67c8a59 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -289,7 +289,7 @@
 
 const void *agesawrapper_locate_module (const CHAR8 name[8])
 {
-	const void* agesa;
+	const void *agesa;
 	const AMD_IMAGE_HEADER* image;
 	const AMD_MODULE_HEADER* module;
 	size_t file_size;
diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h
index 1ed4a4c..bfcd78d 100644
--- a/src/northbridge/amd/pi/agesawrapper_call.h
+++ b/src/northbridge/amd/pi/agesawrapper_call.h
@@ -30,7 +30,7 @@
  * 0x6 = AGESA_CRITICAL
  * 0x7 = AGESA_FATAL
  */
-static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
+static const char *decodeAGESA_STATUS(AGESA_STATUS sret)
 {
 	const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
 					"AGESA_BOUNDS_CHK", "AGESA_ALERT",
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index ed79f45..999d5a8 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -43,7 +43,7 @@
 			+ FspInfo->ImageBase);
 	UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)
 			(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
-	memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+	memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
 }
 
 typedef struct northbridge_intel_fsp_rangeley_config config_t;
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
index 888da8e..eb31655 100644
--- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
@@ -33,7 +33,7 @@
 	UPD_DATA_REGION *UpdDataRgnPtr;
 	VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset  + FspInfo->ImageBase);
 	UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
-	memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+	memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
 }
 
 static void ConfigureDefaultUpdData(UPD_DATA_REGION   *UpdData)
@@ -70,7 +70,7 @@
 	UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr;
 #else
 	MEM_CONFIG MemoryConfig;
-	memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG));
+	memset((void *)&MemoryConfig, 0, sizeof(MEM_CONFIG));
 #endif
 	FspInitParams->NvsBufferPtr = NULL;
 
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 77aba94..0108116 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -54,7 +54,7 @@
 		u8 cmd = pci_read_config8(igd, PCI_COMMAND);
 		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 		pci_write_config8(igd, PCI_COMMAND, cmd);
-		void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
+		void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
 
 		/* clear GTT, 2MB is enough (and should be safe) */
 		memset(bar, 0, 2<<20);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 94d9af8..dcf9b7b 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1786,7 +1786,7 @@
 				       csr.csr.buffer_read_ptr));
 }
 
-static void send_heci_packet(struct mei_header *head, u32 * payload)
+static void send_heci_packet(struct mei_header *head, u32 *payload)
 {
 	int len = (head->length + 3) / 4;
 	int i;
@@ -1803,7 +1803,7 @@
 }
 
 static void
-send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
+send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)
 {
 	struct mei_header head;
 	int maxlen;
@@ -1830,8 +1830,8 @@
 
 /* FIXME: Add timeout.  */
 static int
-recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
-		 u32 * packet_size)
+recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,
+		 u32 *packet_size)
 {
 	union {
 		struct mei_csr csr;
@@ -1877,7 +1877,7 @@
 
 /* FIXME: Add timeout.  */
 static int
-recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size)
+recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)
 {
 	struct mei_header head;
 	int current_position;
@@ -2291,9 +2291,9 @@
 }
 
 static void
-do_fsm(enum state *state, u16 * counter,
-       u8 fail_mask, int margin, int uplimit,
-       u8 * res_low, u8 * res_high, u8 val)
+do_fsm(enum state *state, u16 *counter,
+	u8 fail_mask, int margin, int uplimit,
+	u8 *res_low, u8 *res_high, u8 val)
 {
 	int lane;
 
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index f31f032..66f0a10 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -1845,7 +1845,7 @@
 		MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2;
 		hpet_udelay(1);
 		barrier();
-		strobedata = read32((void*)strobeaddr);
+		strobedata = read32((void *)strobeaddr);
 		barrier();
 		hpet_udelay(1);
 
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 075a872..b90e2d4 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -246,7 +246,7 @@
 };
 
 #if IS_ENABLED(CONFIG_PIRQ_ROUTE)
-void pirq_assign_irqs(const u8 * pirq)
+void pirq_assign_irqs(const u8 *pirq)
 {
 	struct device *lpc;