commit fce128cdfb817eb8f8a88c3a815fb109e8a0a504
author Stefan Reinauer <reinauer@chromium.org> Tue Jul 21 12:52:34 2015 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Fri Oct 30 18:16:28 2015 +0100
tree 4147565a2c47bda465a301b3492e55bebf8a3c50
parent 77a1d1adaec157d6d3542cd92ac2b6cf2dc40938

Hudson: Port to 64bit

Bring http://review.coreboot.org/#/c/10582/ to Hudson

Change-Id: I1ba3047699c304a769215fe901dc3511bf23199d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11022
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/southbridge/amd/agesa/hudson/fadt.c

diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
index cef10b1..14b91d4 100644
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ b/src/southbridge/amd/agesa/hudson/fadt.c
@@ -59,8 +59,16 @@
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
+	if ((uintptr_t)facs > 0xffffffff)
+		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
+	else
+		fadt->firmware_ctrl = (uintptr_t)facs;
+
+	if ((uintptr_t)dsdt > 0xffffffff)
+		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
+	else
+		fadt->dsdt = (uintptr_t)dsdt;
+
 	fadt->model = 0;		/* reserved, should be 0 ACPI 3.0 */
 	fadt->preferred_pm_profile = FADT_PM_PROFILE;
 	fadt->sci_int = 9;		/* HUDSON - IRQ 09 – ACPI SCI */
@@ -138,10 +146,11 @@
 	fadt->res4 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 	fadt->res5 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 
-	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32) dsdt;
-	fadt->x_dsdt_h = 0;
+
+	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
+	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
+	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
+	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
 
 	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_evt_blk.bit_width = 32;

src/southbridge/amd/agesa/hudson/spi.c

diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 95fffb8..9a6f8af 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -49,7 +49,7 @@
 #define AMD_SB_SPI_TX_LEN	8
 #endif
 
-static u32 spibar;
+static uintptr_t spibar;
 
 static inline uint8_t spi_read(uint8_t reg)
 {