diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index e9f5062..e84aa18 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -31,6 +31,11 @@
 	/* Override dev tree settings per board */
 }
 
+void __weak variant_ramstage_init(void)
+{
+	/* Default weak implementation */
+}
+
 static void mainboard_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -56,6 +61,8 @@
 					base_gpios,
 					override_table,
 					override_gpios);
+
+	variant_ramstage_init();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 598600b..94cb2e5 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -38,7 +38,7 @@
 	/* A11 : PCH_SPI_FPMCU_CS_L */
 	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
 	/* A12 : FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* A13 : SUSWARN_L */
 	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
 	/* A14 : ESPI_RST_L */
@@ -133,7 +133,7 @@
 	/* C10 : GPP_10 ==> GPP_C10_TP */
 	PAD_NC(GPP_C10, NONE),
 	/* C11 : GPP_11 ==> EN_FP_RAILS */
-	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
 	/* C12 : GPP_C12 ==> NC */
 	PAD_NC(GPP_C12, NONE),
 	/* C13 : EC_PCH_INT_L */
@@ -398,8 +398,10 @@
 }
 
 /*
- * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
- * as GPO before entering sleep.
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See https://review.coreboot.org/c/coreboot/+/32111 .
  */
 static const struct pad_config default_sleep_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
@@ -408,10 +410,11 @@
 /*
  * GPIO settings before entering S5, which are same as
  * default_sleep_gpio_table but also,
- * turn off EN_PP3300_WWAN.
+ * turn off EN_PP3300_WWAN and FPMCU.
  */
 static const struct pad_config s5_sleep_gpio_table[] = {
-	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
 	PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
 };
 
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index 920e428..1542d9b 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -50,4 +50,7 @@
 /* Modify devictree settings during ramstage. */
 void variant_devtree_update(void);
 
+/* Perform variant specific initialization early on in ramstage. */
+void variant_ramstage_init(void);
+
 #endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc
index fbd69c4..be074b7 100644
--- a/src/mainboard/google/hatch/variants/helios/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc
@@ -17,4 +17,6 @@
 
 romstage-y += memory.c
 bootblock-y += gpio.c
+
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c
index 85eb3fc..456877c 100644
--- a/src/mainboard/google/hatch/variants/helios/gpio.c
+++ b/src/mainboard/google/hatch/variants/helios/gpio.c
@@ -117,8 +117,6 @@
  * needed in this table.
  */
 static const struct pad_config early_gpio_table[] = {
-	/* A12 : FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* B15 : H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : H1_SLAVE_SPI_CLK */
@@ -127,8 +125,6 @@
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
-	/* C11 : GPP_C11 ==> EN_FP_RAILS */
-	PAD_CFG_GPO(GPP_C11, 1, DEEP),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
@@ -150,14 +146,30 @@
 }
 
 /*
- * GPIO settings before entering all sleep states
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See https://review.coreboot.org/c/coreboot/+/32111 .
  */
-static const struct pad_config sleep_gpio_table[] = {
+static const struct pad_config default_sleep_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 };
 
+/*
+ * GPIO settings before entering S5, which are same as
+ * default_sleep_gpio_table but also, turn off FPMCU.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
+};
+
 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 {
-	*num = ARRAY_SIZE(sleep_gpio_table);
-	return sleep_gpio_table;
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
 }
diff --git a/src/mainboard/google/hatch/variants/helios/ramstage.c b/src/mainboard/google/hatch/variants/helios/ramstage.c
new file mode 100644
index 0000000..9b919fc
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/helios/ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_ramstage_init(void)
+{
+	/*
+	 * Enable power to FPMCU, wait for power rail to stabilize,
+	 * and then deassert FPMCU reset.
+	 * Waiting for the power rail to stabilize can take a while,
+	 * a minimum of 400us on Kohaku.
+	 */
+	gpio_output(GPP_C11, 1);
+	mdelay(1);
+	gpio_output(GPP_A12, 1);
+}
diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c
index 827ee0b..9e2d818 100644
--- a/src/mainboard/google/hatch/variants/kindred/gpio.c
+++ b/src/mainboard/google/hatch/variants/kindred/gpio.c
@@ -154,8 +154,6 @@
  * needed in this table.
  */
 static const struct pad_config early_gpio_table[] = {
-	/* A12 : FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* B15 : H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : H1_SLAVE_SPI_CLK */
diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc
index 9cdff32..6bd2973 100644
--- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc
@@ -17,4 +17,6 @@
 romstage-y += memory.c
 
 bootblock-y += gpio.c
+
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c
index 61d3375..f52cc27 100644
--- a/src/mainboard/google/hatch/variants/kohaku/gpio.c
+++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c
@@ -97,8 +97,6 @@
  * needed in this table.
  */
 static const struct pad_config early_gpio_table[] = {
-	/* A12 : FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* B15 : H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : H1_SLAVE_SPI_CLK */
@@ -136,14 +134,30 @@
 }
 
 /*
- * GPIO settings before entering all sleep states
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See https://review.coreboot.org/c/coreboot/+/32111 .
  */
-static const struct pad_config sleep_gpio_table[] = {
+static const struct pad_config default_sleep_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 };
 
+/*
+ * GPIO settings before entering S5, which are same as
+ * default_sleep_gpio_table but also, turn off FPMCU.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
+};
+
 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 {
-	*num = ARRAY_SIZE(sleep_gpio_table);
-	return sleep_gpio_table;
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
 }
diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c
new file mode 100644
index 0000000..9b919fc
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_ramstage_init(void)
+{
+	/*
+	 * Enable power to FPMCU, wait for power rail to stabilize,
+	 * and then deassert FPMCU reset.
+	 * Waiting for the power rail to stabilize can take a while,
+	 * a minimum of 400us on Kohaku.
+	 */
+	gpio_output(GPP_C11, 1);
+	mdelay(1);
+	gpio_output(GPP_A12, 1);
+}