|author||Craig Hesling <email@example.com>||Wed Nov 27 11:50:47 2019 -0800|
|committer||Shelley Chen <firstname.lastname@example.org>||Thu Dec 05 21:27:42 2019 +0000|
hatch: Fix FPMCU pwr/rst gpio handling 1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <email@example.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) <firstname.lastname@example.org> Reviewed-by: Furquan Shaikh <email@example.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case).
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This makes the resulting coreboot images licensed under the GPL, version 2.