commit fbf260a0d5f3b33f32e6d45785cae13ca5515a92
author Felix Singer <felixsinger@posteo.net> Tue Apr 30 16:25:28 2024 +0200
committer Felix Singer <service+coreboot-gerrit@felixsinger.de> Thu May 02 16:07:49 2024 +0000
tree 3987b0faa19c83200865e478ff6a3953eef4c2bf
parent 5ed9fe94972e8383edd7929ccce4d9b73823a362

soc/intel/cannonlake: Clean up device enablement configuration

Clean up by using is_devfn_enabled().

Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/acpi.c

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 9cad4ff..a58c4f0 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -255,10 +255,9 @@
 
 static unsigned long soc_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 	bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
-	const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten;
+	const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
 	if (emit_igd) {
 		unsigned long tmp = current;
 
@@ -268,11 +267,10 @@
 		acpi_dmar_drhd_fixup(tmp, current);
 	}
 
-	struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
 	uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 	bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 
-	if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
+	if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
 		unsigned long tmp = current;
 
 		current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);

src/soc/intel/cannonlake/romstage/fsp_params.c

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 737e7c3..2b25285 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -32,8 +32,7 @@
 	 * Probe for no IGD and disable InternalGfx and panel power to prevent a
 	 * crash in FSP-M.
 	 */
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
+	const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
 	if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
 		/* Set IGD stolen size to 64MB. */
 		m_cfg->InternalGfx = 1;
@@ -90,25 +89,11 @@
 		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
 	}
 
-	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
-	/* If ISH is enabled, enable ISH elements */
-	if (!dev)
-		m_cfg->PchIshEnable = 0;
-	else
-		m_cfg->PchIshEnable = dev->enabled;
+	m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
 
-	/* If HDA is enabled, enable HDA elements */
-	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
-	if (!dev)
-		m_cfg->PchHdaEnable = 0;
-	else
-		m_cfg->PchHdaEnable = dev->enabled;
+	m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
 
-	/* Enable IPU only if the device is enabled */
-	m_cfg->SaIpuEnable = 0;
-	dev = pcidev_path_on_root(SA_DEVFN_IPU);
-	if (dev)
-		m_cfg->SaIpuEnable = dev->enabled;
+	m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
 
 	/* SATA Gen3 strength */
 	for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) {
@@ -136,12 +121,7 @@
 		tconfig->DisableHeciRetry = config->DisableHeciRetry;
 #endif
 
-	/* Enable SMBus controller based on config */
-	dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
-	if (!dev)
-		m_cfg->SmbusEnable = 0;
-	else
-		m_cfg->SmbusEnable = dev->enabled;
+	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
 
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent =