tree 790c11309cf66c926171b8bd03627c84bf0335ab
parent fd4f8911c12cb28467054eb06896bae1e0337df0
author Mario Scheithauer <mario.scheithauer@siemens.com> 1679043774 +0100
committer Lean Sheng Tan <sheng.tan@9elements.com> 1679397561 +0000

mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1

Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3)
and #5 (00:1c.4), the speed must be limit to Gen 1.

BUG=none
TEST=RX signal measured with oscilloscope

Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>