soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index f2fdc7f..620c650 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -342,13 +342,11 @@
help
Disables the output of port80 post codes from PSP.
-config PSP_POSTCODES_ON_ESPI
- bool "Use eSPI bus for PSP post codes"
- default y
- depends on !PSP_DISABLE_POSTCODES
+config PSP_INIT_ESPI
+ bool "Initialize eSPI in PSP Stage 2 Boot Loader"
help
- Select to send PSP port80 post codes on eSPI bus.
- If not selected, PSP port80 codes will be sent on LPC bus.
+ Select to initialize the eSPI controller in the PSP Stage 2 Boot
+ Loader.
config PSP_LOAD_MP2_FW
bool
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 5fda4b0..5708baa0 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -94,7 +94,7 @@
PSP_SOFTFUSE_BITS += 7
endif
-ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y)
+ifeq ($(CONFIG_PSP_INIT_ESPI),y)
PSP_SOFTFUSE_BITS += 15
endif