mb/system76/adl-p: Add Galago Pro 6 as a variant
The Galago Pro 6 (galp6) is an Alder Lake-P board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17
Not working:
- Detection of devices in TBT slot on boot
Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 6911d5c..2e314e6 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -204,6 +204,7 @@
- [Darter Pro 8](system76/darp8.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
+- [Galago Pro 6](system76/galp6.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Lemur Pro 9](system76/lemp9.md)
diff --git a/Documentation/mainboard/system76/galp6.md b/Documentation/mainboard/system76/galp6.md
new file mode 100644
index 0000000..e519dc3
--- /dev/null
+++ b/Documentation/mainboard/system76/galp6.md
@@ -0,0 +1,61 @@
+# System76 Galago Pro 6 (galp6)
+
+## Specs
+
+- CPU
+ - Intel Core i5-1240P
+ - Intel Core i7-1260P
+- EC
+ - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+ - Intel Iris Xe Graphics
+ - eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
+ - 1x HDMI 2.1
+ - 1x DisplayPort 1.4 over USB-C
+- Memory
+ - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+ - Gigabit Ethernet
+ - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+ - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
+ - USB-C charging, compatible with 90W+ chargers
+ - 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
+- Sound
+ - Realtek ALC256 codec
+ - Internal speakers and microphone
+ - Combined 3.5mm headphone/microphone jack
+ - HDMI, USB-C DisplayPort audio
+- Storage
+ - M.2 PCIe NVMe Gen 4 SSD
+ - MicroSD card reader (OZ711LV2)
+- USB
+ - 1x USB-C Type-C with Thunderbolt 4
+ - 1x USB 3.2 (Gen 2) Type-C
+ - 2x USB 3.2 (Gen 1) Type-A
+- Dimensions
+ - 32.49cm x 22.5cm x 1.82cm, 1.45kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type | Value |
++=====================+=====================+
+| Socketed flash | no |
++---------------------+---------------------+
+| Vendor | Macronix |
++---------------------+---------------------+
+| Model | MX25L25673G |
++---------------------+---------------------+
+| Size | 32 MiB |
++---------------------+---------------------+
+| Package | WSON-8 |
++---------------------+---------------------+
+| Internal flashing | yes |
++---------------------+---------------------+
+| External flashing | yes |
++---------------------+---------------------+
+```
+
+The flash chip (U43) is left of the wireless card.
diff --git a/src/mainboard/system76/adl-p/Kconfig b/src/mainboard/system76/adl-p/Kconfig
index e9ac901..80c42a8 100644
--- a/src/mainboard/system76/adl-p/Kconfig
+++ b/src/mainboard/system76/adl-p/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_SYSTEM76_DARP8
+if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -28,18 +28,22 @@
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
+ default "galp6" if BOARD_SYSTEM76_GALP6
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
+ default "galp6" if BOARD_SYSTEM76_GALP6
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
+ default "Galago Pro" if BOARD_SYSTEM76_GALP6
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
+ default "galp6" if BOARD_SYSTEM76_GALP6
config CBFS_SIZE
default 0xA00000
diff --git a/src/mainboard/system76/adl-p/Kconfig.name b/src/mainboard/system76/adl-p/Kconfig.name
index 9533451..5e3aee3 100644
--- a/src/mainboard/system76/adl-p/Kconfig.name
+++ b/src/mainboard/system76/adl-p/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_SYSTEM76_DARP8
bool "darp8"
+
+config BOARD_SYSTEM76_GALP6
+ bool "galp6"
diff --git a/src/mainboard/system76/adl-p/variants/galp6/board_info.txt b/src/mainboard/system76/adl-p/variants/galp6/board_info.txt
new file mode 100644
index 0000000..d7ee3f4
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/board_info.txt
@@ -0,0 +1,2 @@
+Board name: galp6
+Release year: 2022
diff --git a/src/mainboard/system76/adl-p/variants/galp6/data.vbt b/src/mainboard/system76/adl-p/variants/galp6/data.vbt
new file mode 100644
index 0000000..d58825f
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/adl-p/variants/galp6/gpio.c b/src/mainboard/system76/adl-p/variants/galp6/gpio.c
new file mode 100644
index 0000000..b73f06b
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Group GPD ------- */
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+ PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+ PAD_NC(GPP_A6, NONE),
+ PAD_NC(GPP_A7, NONE),
+ PAD_NC(GPP_A8, NONE),
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+ PAD_NC(GPP_A11, NONE),
+ PAD_CFG_GPI(GPP_A12, NONE, DEEP), // SATAGP1
+ PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+ // GPP_A14 (DGPU_PWR_EN) configured in bootblock
+ PAD_NC(GPP_A15, NONE), // USB_OC2#
+ PAD_NC(GPP_A16, NONE), // USB_OC3#
+ PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+ PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+ PAD_NC(GPP_A20, NONE),
+ PAD_NC(GPP_A21, NONE),
+ PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
+ PAD_NC(GPP_A23, NONE),
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+ // GPP_B2 (DGPU_RST#_PCH) configured in bootblock
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+ PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+ PAD_NC(GPP_B5, NONE), // I2C2_SDA (Pantone)
+ PAD_NC(GPP_B6, NONE), // I2C2_SCL (Pantone)
+ PAD_NC(GPP_B7, NONE),
+ PAD_NC(GPP_B8, NONE),
+ // GPP_B9 missing
+ // GPP_B10 missing
+ PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+ // GPP_B19 missing
+ // GPP_B20 missing
+ // GPP_B21 missing
+ // GPP_B22 missing
+ PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+ PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+ PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
+ // GPP_C8 missing
+ // GPP_C9 missing
+ // GPP_C10 missing
+ // GPP_C11 missing
+ // GPP_C12 missing
+ // GPP_C13 missing
+ // GPP_C14 missing
+ // GPP_C15 missing
+ // GPP_C16 missing
+ // GPP_C17 missing
+ // GPP_C18 missing
+ // GPP_C19 missing
+ // GPP_C20 missing
+ // GPP_C21 missing
+ // GPP_C22 missing
+ // GPP_C23 missing
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+ PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+ PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+ PAD_NC(GPP_D3, NONE),
+ PAD_NC(GPP_D4, NONE),
+ // GPP_D5 (SSD1_CLKREQ#) programmed by FSP
+ PAD_NC(GPP_D6, NONE),
+ // GPP_D7 (WLAN_CLKREQ#) programmed by FSP
+ // GPP_D8 (PEG_CLKREQ#) programmed by FSP
+ PAD_NC(GPP_D9, NONE),
+ PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap
+ PAD_NC(GPP_D11, NONE),
+ PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap
+ PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+ PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD1_PWR_EN#
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+ _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+ PAD_NC(GPP_E2, NONE),
+ PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN
+ PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+ PAD_NC(GPP_E5, NONE), // DEVSLP1
+ PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+ PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+ PAD_NC(GPP_E10, NONE), // strap
+ PAD_NC(GPP_E11, NONE), // strap
+ PAD_NC(GPP_E12, NONE),
+ PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+ // GPP_E18 (TBT_LSX0_TXD) configured by FSP
+ // GPP_E19 (TBT_LSX0_RXD) configured by FSP
+ PAD_NC(GPP_E20, NONE),
+ PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap
+ PAD_NC(GPP_E22, NONE),
+ PAD_NC(GPP_E23, NONE),
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+ // GPP_F5 (CNVI_CLKREQ) programmed by FSP
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+ PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
+ // GPP_F8 missing
+ PAD_NC(GPP_F9, NONE),
+ PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#
+ PAD_CFG_GPI(GPP_F11, NONE, DEEP), // BOARD_ID3
+ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP), // BOARD_ID1
+ PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID2
+ PAD_CFG_GPO(GPP_F16, 1, DEEP), // GPU_EVENT#
+ PAD_NC(GPP_F17, NONE), // GPIO_CARD_PWR
+ PAD_CFG_GPO(GPP_F18, 0, DEEP), // dGPU_OVRM
+ // GPP_F19 (LAN_CLKREQ#) programmed by FSP
+ PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST#
+ PAD_NC(GPP_F21, NONE),
+ PAD_NC(GPP_F22, NONE),
+ PAD_NC(GPP_F23, NONE),
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_NC(GPP_H0, NONE),
+ PAD_NC(GPP_H1, NONE),
+ PAD_NC(GPP_H2, NONE),
+ PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // T_SDA (Touchpad)
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // T_SCL (Touchpad)
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (TBT)
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (TBT)
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+ // GPP_H10 (UART2_RXD) configured in bootblock
+ // GPP_H11 (UART2_TXD) configured in bootblock
+ PAD_NC(GPP_H12, NONE),
+ PAD_NC(GPP_H13, NONE),
+ // GPP_H14 missing
+ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+ // GPP_H16 missing
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+ PAD_NC(GPP_H19, NONE),
+ PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
+ PAD_NC(GPP_H21, NONE),
+ PAD_NC(GPP_H22, NONE),
+ // GPP_H23 (CARD_CLKREQ#) programmed by FSP
+
+ /* ------- GPIO Group GPP_R ------- */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+ PAD_NC(GPP_R5, NONE),
+ PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPC_DMIC_CLK
+ PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPC_DMIC_DATA
+
+ /* ------- GPIO Group GPP_S ------- */
+ PAD_NC(GPP_S0, NONE),
+ PAD_NC(GPP_S1, NONE),
+ PAD_NC(GPP_S2, NONE),
+ PAD_NC(GPP_S3, NONE),
+ PAD_NC(GPP_S4, NONE),
+ PAD_NC(GPP_S5, NONE),
+ PAD_NC(GPP_S6, NONE),
+ PAD_NC(GPP_S7, NONE),
+
+ /* ------- GPIO Group GPP_T ------- */
+ PAD_NC(GPP_T2, NONE),
+ PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c b/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c
new file mode 100644
index 0000000..66577bd
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+ PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART2_RXD (actually UART0)
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART2_TXD (actually UART0)
+};
+
+void mainboard_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
new file mode 100644
index 0000000..ff2dc8e
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC256 */
+ 0x10ec0256, /* Vendor ID */
+ 0x15584041, /* Subsystem ID */
+ 11, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x15584041),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
new file mode 100644
index 0000000..fc93fdc
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
@@ -0,0 +1,181 @@
+chip soc/intel/alderlake
+ register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+ .tdp_pl1_override = 28,
+ .tdp_pl2_override = 60,
+ .tdp_pl4 = 90,
+ }"
+
+ # GPE configuration
+ register "pmc_gpe0_dw0" = "PMC_GPP_A"
+ register "pmc_gpe0_dw1" = "PMC_GPP_R"
+ register "pmc_gpe0_dw2" = "PMC_GPD"
+
+ device domain 0 on
+ subsystemid 0x1558 0x4041 inherit
+
+ device ref pcie4_0 on
+ # PCIe PEG0 x4, Clock 0 (SSD1)
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ device ref tcss_xhci on
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 TBT Type-C""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref xhci on
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+ # ACPI
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 J_USB3_2""
+ register "type" = "UPC_TYPE_A"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 J_TYPEC1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 J_USB3_1""
+ register "type" = "UPC_TYPE_A"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Fingerprint""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 J_TYPEC2""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 J_USB3_2""
+ register "type" = "UPC_TYPE_A"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 J_USB3_1""
+ register "type" = "UPC_TYPE_A"
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 J_TYPEC1""
+ register "type" = "UPC_TYPE_A"
+ device ref usb3_port4 on end
+ end
+ end
+ end
+ end
+ device ref i2c0 on
+ # Touchpad I2C bus
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN0412""
+ register "generic.desc" = ""ELAN Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""FTCS1000""
+ register "generic.desc" = ""FocalTech Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 38 on end
+ end
+ end
+ device ref sata off end
+ device ref pcie_rp5 on
+ # PCIe RP#5 x1, Clock 2 (WLAN)
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "2" # WLAN_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp9 on
+ # PCIe RP#9 x1, Clock 5 (CARD)
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp10 on
+ # PCIe RP#10 x1, Clock 6 (GLAN)
+ register "pch_pcie_rp[PCH_RP(10)]" = "{
+ .clk_src = 6,
+ .clk_req = 6,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
+ register "srcclk_pin" = "6" # LAN_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ # J_TYPEC2
+ use usb2_port6 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/system76/adl-p/variants/galp6/romstage.c b/src/mainboard/system76/adl-p/variants/galp6/romstage.c
new file mode 100644
index 0000000..3d6a5fb
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/galp6/romstage.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const struct mb_cfg board_cfg = {
+ .type = MEM_TYPE_DDR4,
+ };
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_DIMM_MODULE,
+ .smbus = {
+ [0] = { .addr_dimm[0] = 0x50, },
+ [1] = { .addr_dimm[0] = 0x52, },
+ },
+ };
+ const bool half_populated = false;
+
+ mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+ mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+ mupd->FspmConfig.GpioOverride = 0;
+
+ memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}