sandy/ivy native: dedup romstage.c main()
Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7127
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 4d1684d..83be0c7 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -37,12 +37,10 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cbfs.h>
-#include "gpio.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* T520 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -60,7 +58,7 @@
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -109,85 +107,24 @@
RCBA32(BUC) = 0;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 }, /* P0 left dual conn, OC 0 */
+ { 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
+ { 1, 2, -1 }, /* P2: wimax / WLAN */
+ { 1, 1, -1 }, /* P3: WWAN, no OC */
+ { 1, 1, -1 }, /* P4: smartcard, no OC */
+ { 1, 1, -1 }, /* P5: ExpressCard, no OC */
+ { 0, 2, -1 }, /* P6: empty */
+ { 0, 2, -1 }, /* P7: to touch panel, no OC */
+ { 1, 1, 4 }, /* P8: left dual conn, OC4 */
+ { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
+ { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 2, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 1, -1 }, /* P12: docking, no OC */
+ { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
+};
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&t520_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 1, 0 }, /* P0 left dual conn, OC 0 */
- { 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
- { 1, 2, -1 }, /* P2: wimax / WLAN */
- { 1, 1, -1 }, /* P3: WWAN, no OC */
- { 1, 1, -1 }, /* P4: smartcard, no OC */
- { 1, 1, -1 }, /* P5: ExpressCard, no OC */
- { 0, 2, -1 }, /* P6: empty */
- { 0, 2, -1 }, /* P7: to touch panel, no OC */
- { 1, 1, 4 }, /* P8: left dual conn, OC4 */
- { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
- { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
- { 1, 2, -1 }, /* P11: bluetooth, no OC. */
- { 1, 1, -1 }, /* P12: docking, no OC */
- { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset(spd, 0, sizeof(spd));
- read_spd(&spd[0], 0x50);
- read_spd(&spd[2], 0x51);
-
- init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
+void mainboard_get_spd(spd_raw_data *spd) {
+ read_spd (&spd[0], 0x50);
+ read_spd (&spd[2], 0x51);
}