mb/google/guybrush: use gpio.h include
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/guybrush/ec.c b/src/mainboard/google/guybrush/ec.c
index f62ca20..fdfc6e3 100644
--- a/src/mainboard/google/guybrush/ec.c
+++ b/src/mainboard/google/guybrush/ec.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
-#include <amdblocks/gpio.h>
#include <amdblocks/smi.h>
#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
#include <soc/smi.h>
#include <variant/ec.h>
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index b2a7e64..49fe617 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -3,8 +3,8 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <gpio.h>
#include <soc/platform_descriptors.h>
-#include <soc/gpio.h>
#include <types.h>
/* All PCIe Resets are handled in coreboot */
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 595f680..cb56515 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -4,7 +4,6 @@
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <gpio.h>
-#include <soc/gpio.h>
/* GPIO configuration in ramstage */
/* Please make sure that *ALL* GPIOs are configured in this table */
diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c
index fe30e15..84fe732 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c
@@ -2,7 +2,7 @@
#include <baseboard/variants.h>
#include <device/device.h>
-#include <soc/gpio.h>
+#include <gpio.h>
bool __weak variant_has_pcie_wwan(void)
{
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
index 34e2edd..3cbb9ee 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
@@ -6,6 +6,7 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
+/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
#include <soc/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h
index 90f4420..56552a6 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h
@@ -3,6 +3,7 @@
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
+/* Since this ends up being included in dsdt.asl, <gpio.h> can't be included instead */
#include <soc/gpio.h>
/* SPI Write protect */
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index 24c03b0..9f99b9f 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -3,7 +3,7 @@
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__
-#include <amdblocks/gpio.h>
+#include <gpio.h>
#include <soc/pci_devs.h>
#include <platform_descriptors.h>
diff --git a/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c
index aa8eaa0..2f3e426 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <boardid.h>
+#include <gpio.h>
#include <security/tpm/tis.h>
-#include <soc/gpio.h>
int tis_plat_irq_status(void)
{
diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c
index 571cbb4..73081ed 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/gpio.c
+++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c
@@ -3,7 +3,6 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
-#include <soc/gpio.h>
/* This table is used by guybrush variant */
static const struct soc_amd_gpio override_ramstage_gpio_table[] = {
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index dcbda20..60013b1 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -4,7 +4,6 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <gpio.h>
-#include <soc/gpio.h>
/* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c
index 974e357..394270c 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/variant.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c
@@ -3,8 +3,8 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <device/device.h>
-#include <soc/gpio.h>
#include <amdblocks/cpu.h>
+#include <gpio.h>
bool variant_has_pcie_wwan(void)
{
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
index c9f637c..1c415bf 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
@@ -4,7 +4,6 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <gpio.h>
-#include <soc/gpio.h>
/* This table is used by nipperkin variant with board version < 2. */
static const struct soc_amd_gpio bid1_override_gpio_table[] = {
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c
index c2f4fbf..247c132 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c
@@ -5,7 +5,7 @@
#include <device/device.h>
#include <drivers/i2c/tpm/chip.h>
#include <drivers/uart/acpi/chip.h>
-#include <soc/gpio.h>
+#include <gpio.h>
static void cr50_devtree_update(void)
{
diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c
index eb94e21..5b44c4b 100644
--- a/src/mainboard/google/guybrush/verstage.c
+++ b/src/mainboard/google/guybrush/verstage.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h>
-#include <amdblocks/gpio.h>
#include <arch/io.h>
#include <baseboard/variants.h>
+#include <gpio.h>
#include <psp_verstage.h>
#include <security/vboot/vboot_common.h>
#include <soc/southbridge.h>