vc/amd/opensil/genoa_poc/openSIL: Add openSIL code as submodule
This is a RW mirror of AMD's openSIL for Genoa with additions from
Arthur Heymans.
- origin/openSIL/main from
https://github.com/openSIL/openSIL.git
- origin/ArthurHeymans/64b_public from
https://github.com/ArthurHeymans/openSIL.git
The current main branch starts with Arthur's branch and adds 5 commits
from the AMD's openSIL repo.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8917edf3a6a8493ffa9230902cafcc6234d3d571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/.gitmodules b/.gitmodules
index 6f62952..5241f58 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -65,3 +65,6 @@
path = util/goswid
url = ../goswid
branch = trunk
+[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
+ path = src/vendorcode/amd/opensil/genoa_poc/opensil
+ url = ../opensil_genoa_poc.git
diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil b/src/vendorcode/amd/opensil/genoa_poc/opensil
new file mode 160000
index 0000000..d81517e
--- /dev/null
+++ b/src/vendorcode/amd/opensil/genoa_poc/opensil
@@ -0,0 +1 @@
+Subproject commit d81517ec318455de7c18070340e891e120e22bfb