diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h
index ef755ea..ca30f38 100644
--- a/src/northbridge/amd/agesa/BiosCallOuts.h
+++ b/src/northbridge/amd/agesa/BiosCallOuts.h
@@ -6,18 +6,18 @@
 #include <Porting.h>
 #include <AGESA.h>
 
-AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-AGESA_STATUS agesa_Reset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt);
 
-AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
-AGESA_STATUS HeapManagerCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS HeapManagerCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 typedef struct {
 	UINT32 CalloutName;
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h
index 183a330..8b62ae9 100644
--- a/src/northbridge/amd/agesa/agesa_helper.h
+++ b/src/northbridge/amd/agesa/agesa_helper.h
@@ -19,8 +19,8 @@
 	PICK_CDIT,      /* Component Locality Distance Information table */
 };
 
-void agesawrapper_setlateinitptr (void *Late);
-void *agesawrapper_getlateinitptr (int pick);
+void agesawrapper_setlateinitptr(void *Late);
+void *agesawrapper_getlateinitptr(int pick);
 
 void amd_initcpuio(void);
 void amd_initenv(void);
diff --git a/src/northbridge/amd/agesa/dimmSpd.h b/src/northbridge/amd/agesa/dimmSpd.h
index dbcb106..578df0d 100644
--- a/src/northbridge/amd/agesa/dimmSpd.h
+++ b/src/northbridge/amd/agesa/dimmSpd.h
@@ -4,7 +4,7 @@
 #define _DIMMSPD_H_
 
 AGESA_STATUS
-AmdMemoryReadSPD (IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
+AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
 
 int hudson_readSpd(int spdAddress, char *buf, size_t len);
 
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index 36e5fd9..dfb42ae 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -34,7 +34,7 @@
 	struct device *dev = pcidev_on_root(0x18, 2);
 #endif
 	u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
-	if (mct_cfg_lo & (1<<19)) {
+	if (mct_cfg_lo & (1 << 19)) {
 		printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
 		system_reset();
 	}
diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c
index 2cc9bf5..cf88cfa 100644
--- a/src/northbridge/amd/pi/00730F01/acpi_tables.c
+++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c
@@ -9,11 +9,11 @@
 	current = acpi_create_madt_lapics(current);
 
 	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS,
 					   IO_APIC_ADDR, 0);
 
 	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1,
 					   0xFEC20000, 24);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c
index 42dd5a2..c24466e 100644
--- a/src/northbridge/amd/pi/00730F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c
@@ -11,7 +11,7 @@
 
 #include <northbridge/amd/pi/dimmSpd.h>
 
-AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
+AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
 	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
@@ -37,7 +37,7 @@
 	if (spdAddress == 0)
 		return AGESA_ERROR;
 
-	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
+	int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128);
 	if (err)
 		return AGESA_ERROR;
 	return AGESA_SUCCESS;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 5fbd0e7..b1df81a 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -51,7 +51,7 @@
 	if (node_nums)
 		return node_nums;
 
-	node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
+	node_nums = ((pci_read_config32(get_mc_dev(), 0x60) >> 4) & 7) + 1; //NodeCnt[2:0]
 
 	return node_nums;
 }
@@ -65,7 +65,7 @@
 		__f2_dev[i] = get_node_pci(i, 2);
 		__f4_dev[i] = get_node_pci(i, 4);
 		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
-			fx_devs = i+1;
+			fx_devs = i + 1;
 	}
 	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
 		die("Cannot find 0:0x18.[0|1]\n");
@@ -123,7 +123,7 @@
 {
 	u32 val;
 
-	val =  1 | (nodeid<<4) | (linkn<<12);
+	val =  1 | (nodeid << 4) | (linkn << 12);
 	/* it will routing
 	 * (1)mmio 0xa0000:0xbffff
 	 * (2)io   0x3b0:0x3bb, 0x3c0:0x3df
@@ -151,7 +151,7 @@
 		resource_t basek, limitk;
 		if (!get_dram_base_limit(0, &basek, &limitk))
 			return;
-		mmio_resource_kb(dev, index++, limitk, 16*1024);
+		mmio_resource_kb(dev, index++, limitk, 16 * 1024);
 	}
 }
 
@@ -180,7 +180,7 @@
 	struct bus *link;
 	unsigned int sblink;
 
-	sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1
+	sblink = (pci_read_config32(get_mc_dev(), 0x64) >> 8) & 7; // don't forget sublink1
 
 	/* find out which link the VGA card is connected,
 	 * we only deal with the 'first' vga card */
@@ -189,7 +189,7 @@
 #if CONFIG(MULTIPLE_VGA_ADAPTERS)
 			extern struct device *vga_pri; // the primary vga device, defined in device.c
 			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
-					link->secondary,link->subordinate);
+					link->secondary, link->subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if ((vga_pri->bus->secondary >= link->secondary) &&
 			    (vga_pri->bus->secondary <= link->subordinate))
@@ -220,7 +220,7 @@
 
 static void northbridge_init(struct device *dev)
 {
-	setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
+	setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1);
 }
 
 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@@ -591,7 +591,7 @@
 	/* IVRS */
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:   * IVRS at %lx\n", current);
-	ivrs = (acpi_ivrs_t *) current;
+	ivrs = (acpi_ivrs_t *)current;
 	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
 	current += ivrs->header.length;
 	acpi_add_table(rsdp, ivrs);
@@ -599,10 +599,10 @@
 	/* SRAT */
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
 	if (srat != NULL) {
 		memcpy((void *)current, srat, srat->header.length);
-		srat = (acpi_srat_t *) current;
+		srat = (acpi_srat_t *)current;
 		current += srat->header.length;
 		acpi_add_table(rsdp, srat);
 	} else {
@@ -612,10 +612,10 @@
 	/* SLIT */
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
 	if (slit != NULL) {
 		memcpy((void *)current, slit, slit->header.length);
-		slit = (acpi_slit_t *) current;
+		slit = (acpi_slit_t *)current;
 		current += slit->header.length;
 		acpi_add_table(rsdp, slit);
 	} else {
@@ -625,10 +625,10 @@
 	/* ALIB */
 	current = ALIGN(current, 16);
 	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
-	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
 	if (alib != NULL) {
 		memcpy((void *)current, alib, alib->length);
-		alib = (acpi_header_t *) current;
+		alib = (acpi_header_t *)current;
 		current += alib->length;
 		acpi_add_table(rsdp, (void *)alib);
 	}
@@ -640,17 +640,17 @@
 	/* SSDT */
 	current   = ALIGN(current, 16);
 	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
 	if (ssdt != NULL) {
 		patch_ssdt_processor_scope(ssdt);
 		memcpy((void *)current, ssdt, ssdt->length);
-		ssdt = (acpi_header_t *) current;
+		ssdt = (acpi_header_t *)current;
 		current += ssdt->length;
 	}
 	else {
 		printk(BIOS_DEBUG, "  AGESA PState table NULL. Skipping.\n");
 	}
-	acpi_add_table(rsdp,ssdt);
+	acpi_add_table(rsdp, ssdt);
 
 	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 	return current;
@@ -742,7 +742,7 @@
 			continue; // no memory on this node
 		hole = pci_read_config32(__f1_dev[i], 0xf0);
 		if (hole & 2) { // we find the hole
-			mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+			mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
 			mem_hole.node_id = i; // record the node No with hole
 			break; // only one hole
 		}
@@ -757,7 +757,7 @@
 			resource_t base_k, limit_k;
 			if (!get_dram_base_limit(i, &base_k, &limit_k))
 				continue; // no memory on this node
-			if (base_k > 4 *1024 * 1024) break; // don't need to go to check
+			if (base_k > 4 * 1024 * 1024) break; // don't need to go to check
 			if (limitk_pri != base_k) { // we find the hole
 				mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G
 				mem_hole.node_id = i;
@@ -822,7 +822,7 @@
 				   i, basek, limitk, sizek);
 
 		/* split the region to accommodate pci memory space */
-		if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
+		if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
 			if (basek <= mmio_basek) {
 				unsigned int pre_sizek;
 				pre_sizek = mmio_basek - basek;
@@ -833,13 +833,13 @@
 				}
 				basek = mmio_basek;
 			}
-			if ((basek + sizek) <= 4*1024*1024) {
+			if ((basek + sizek) <= 4 * 1024 * 1024) {
 				sizek = 0;
 			}
 			else {
 				uint64_t topmem2 = amd_topmem2();
-				basek = 4*1024*1024;
-				sizek = topmem2/1024 - basek;
+				basek = 4 * 1024 * 1024;
+				sizek = topmem2 / 1024 - basek;
 			}
 		}
 
diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h
index dbcb106..578df0d 100644
--- a/src/northbridge/amd/pi/dimmSpd.h
+++ b/src/northbridge/amd/pi/dimmSpd.h
@@ -4,7 +4,7 @@
 #define _DIMMSPD_H_
 
 AGESA_STATUS
-AmdMemoryReadSPD (IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
+AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
 
 int hudson_readSpd(int spdAddress, char *buf, size_t len);