commit | f99f589ea9df2aca92d8b322094a551f98c64b67 | [log] [tgz] |
---|---|---|
author | Jes Klinke <jbk@google.com> | Tue Dec 01 14:43:31 2020 -0800 |
committer | Patrick Georgi <pgeorgi@google.com> | Tue Dec 08 16:54:56 2020 +0000 |
tree | cf821593d6eace5b07212468cd95e3681712c40a | |
parent | 9a1583b0302595a3427288c0ad48be8068d216fa [diff] |
drivers/i2c/tpm: Unconditionally allow I2C TPM ACPI node DRIVER_I2C_TPM_ACPI is used to enable the "driver" needed for coreboot to present a TPM node in the devicetree. It would usually only do so, if coreboot itself is communicating with the TPM via I2C (I2C_TPM). However, technically, there is no dependency. In order to not show the ACPI option in menuconfig if the board is not using I2C, a dependency was declared in Kconfig. However, the same can be achieved without making it an error to manually declare DRIVER_I2C_TPM_ACPI without I2C_TPM. For Volteer, we have just such a need, since it has two "sub-variants" sharing the same overridetree.cb, one having SPI TPM and another having I2C TPM. The former will have a disabled ACPI node representing the I2C TPM, while its Kconfig is such that coreboot itself does not have I2C TPM support. In order to export even a disabled ACPI node representing the I2C connected TPM, coreboot needs DRIVER_I2C_TPM_ACPI. Hence, that will have to be enabled in a case where coreboot does not have I2C_TPM (for one of the two sub-variants, namely volteer2). BUG=b:173461736 TEST=Tested as part of next CL in chain Change-Id: I9717f6b68afd90fbc294fbbd2a5b8d0c6ee9ae55 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48222 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.