mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PM
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index f78fe2c..cade987 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -40,6 +40,16 @@
register "gen3_dec" = "0x00fc0901"
register "gen4_dec" = "0x000c0081"
+ # This disabled autonomous GPIO power management, otherwise
+ # old cr50 FW only supports short pulses; need to clarify
+ # the minimum PCH IRQ pulse width with Intel, b/180111628
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
+ register "gpio_pm[COMM_5]" = "0"
+
register "PrmrrSize" = "0"
# Enable PCH PCIE RP 5 using CLK 2