nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers
Several registers have been copy-pasted from i945 and do not exist on
Sandy Bridge. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 9db5ae3..5318d0b 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -87,9 +87,6 @@
#define EPVC1RCTL 0x020 /* 32bit */
#define EPVC1RSTS 0x026 /* 16bit */
-#define EPVC1MTS 0x028 /* 32bit */
-#define EPVC1IST 0x038 /* 64bit */
-
#define EPESD 0x044 /* 32bit */
#define EPLE1D 0x050 /* 32bit */
@@ -97,8 +94,6 @@
#define EPLE2D 0x060 /* 32bit */
#define EPLE2A 0x068 /* 64bit */
-#define PORTARB 0x100 /* 256bit */
-
/*
* DMIBAR
*/
@@ -110,27 +105,30 @@
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */
-
#define DMIPVCCCTL 0x00c /* 16bit */
#define DMIVC0RCAP 0x010 /* 32bit */
#define DMIVC0RCTL 0x014 /* 32bit */
#define DMIVC0RSTS 0x01a /* 16bit */
-#define VC0NP 0x2
+#define VC0NP (1 << 1)
#define DMIVC1RCAP 0x01c /* 32bit */
#define DMIVC1RCTL 0x020 /* 32bit */
#define DMIVC1RSTS 0x026 /* 16bit */
-#define VC1NP 0x2
+#define VC1NP (1 << 1)
+#define DMIVCPRCAP 0x028 /* 32bit */
#define DMIVCPRCTL 0x02c /* 32bit */
-
#define DMIVCPRSTS 0x032 /* 16bit */
-#define VCPNP 0x2
+#define VCPNP (1 << 1)
-#define DMIVCMRCTL 0x0038 /* 32 bit */
-#define DMIVCMRSTS 0x003e /* 16 bit */
-#define VCMNP 0x2
+#define DMIVCMRCAP 0x034 /* 32bit */
+#define DMIVCMRCTL 0x038 /* 32bit */
+#define DMIVCMRSTS 0x03e /* 16bit */
+#define VCMNP (1 << 1)
+
+#define DMIRCLDECH 0x040 /* 32bit */
+#define DMIESD 0x044 /* 32bit */
#define DMILE1D 0x050 /* 32bit */
#define DMILE1A 0x058 /* 64bit */
@@ -141,12 +139,15 @@
#define DMILCTL 0x088 /* 16bit */
#define DMILSTS 0x08a /* 16bit */
#define TXTRN (1 << 11)
-#define DMICTL1 0x0f0 /* 32bit */
-#define DMICTL2 0x0fc /* 32bit */
-#define DMICC 0x208 /* 32bit */
+#define DMILCTL2 0x098 /* 16bit */
+#define DMILSTS2 0x09a /* 16bit */
-#define DMIDRCCFG 0xeb4 /* 32bit */
+#define DMIUESTS 0x1c4 /* 32bit */
+#define DMICESTS 0x1d0 /* 32bit */
+
+#define DMIL0SLAT 0x22c /* 32bit */
+#define DMILLTC 0x238 /* 32bit */
#ifndef __ASSEMBLER__