tree 7ded07db717e532a726f3d4499c68a759f6ed403
parent ef5f7ee696097174f9d1f01e9b04ea8f1354cfe0
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1639692435 -0700
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1641585569 +0000

soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs

The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>