tree 0d291886666cb29772d0ab2eb41d6afa49804bdf
parent 0cdcdc736ea28be7bfc6eabdac2430ecf6ee409c
author Sridhar Siricilla <sridhar.siricilla@intel.com> 1623081480 +0530
committer Patrick Georgi <pgeorgi@google.com> 1623396766 +0000

soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"

Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all
ADL-P and ADL-M Silicon CPUID macros and defines generic name
"Alderlake Platform" as macro value. Also, this will avoid log ADL-M  for
ADL-P CPU and vice-versa. Although currently name field of "cpu_table"
points to only "Alderlake Platform, but it is retained asa placeholder in
future difference platforms.

Please refer EDS doc# 619501 for more details.

The macros are renamed as below:
CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0
CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1
CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2

TEST=Verify boot on Brya. After change, relevent coreboot logs appear as
below:

CPU: ID 906a1, Alderlake Platform, ucode: 00000119
CPU: AES supported, TXT supported, VT supported
MCH: device id 4601 (rev 03) is Alderlake-P
PCH: device id 5181 (rev 00) is Alderlake-P SKU
IGD: device id 46b0 (rev 04) is Alderlake P GT2

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>