arch/riscv: Add misc.c to bootblock/romstage to get udelay()

The uart8250mem driver needs it.

Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6784d9b..4521dcb 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -34,6 +34,7 @@
 bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
+bootblock-y += misc.c
 bootblock-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -57,6 +58,7 @@
 romstage-y += boot.c
 romstage-y += stages.c
 romstage-y += rom_media.c
+romstage-y += misc.c
 romstage-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \