tree 60f9b4a81be8455e6ed8a67246cb884c9198b30e
parent 78790c872c8bae4d0fc2cc4614fa9619c69116cd
author Chris Wang <chris.wang@amd.corp-partner.google.com> 1682509685 +0800
committer Martin L Roth <gaumless@gmail.com> 1682606438 +0000

soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment

Add UPD parameter for eDP power sequence adjustment.

The edp_panel_t9_ms parameter is set for bloff to varybloff.

BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>