diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 5421725..fa472b1 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -326,6 +326,12 @@
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
 			0x00000000,,, PM01)
 
+	// PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits
+	QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+			0x00000000,,, PM02)
+
 	// TPM Area (0xfed40000-0xfed44fff)
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
@@ -333,6 +339,9 @@
 			0x00005000,,, TPMR)
 })
 
+External (\A4GS, IntObj)
+External (\A4GB, IntObj)
+
 Method (_CRS, 0, Serialized)
 {
 	// Find PCI resource area in MCRS
@@ -359,5 +368,15 @@
 	PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
 	PLEN = PMAX - PMIN + 1
 
+	If (A4GS != 0) {
+		CreateQwordField(MCRS, ^PM02._MIN, MMIN)
+		CreateQwordField(MCRS, ^PM02._MAX, MMAX)
+		CreateQwordField(MCRS, ^PM02._LEN, MLEN)
+		/* Set 64bit MMIO resource base and length */
+		MLEN = \A4GS
+		MMIN = \A4GB
+		MMAX = MMIN + MLEN - 1
+	}
+
 	Return (MCRS)
 }
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index fe769f9..1bc812a 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/cpu.h>
 #include <console/console.h>
 #include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <commonlib/helpers.h>
 #include <device/pci_ops.h>
 #include <delay.h>
@@ -82,6 +84,14 @@
 	}
 }
 
+static uint64_t get_touud(const struct device *dev)
+{
+	uint64_t touud = pci_read_config32(dev, TOUUD + 4);
+	touud <<= 32;
+	touud |= pci_read_config32(dev, TOUUD);
+	return touud;
+}
+
 static void mc_read_resources(struct device *dev)
 {
 	uint64_t tom, me_base, touud;
@@ -123,9 +133,7 @@
 	 */
 
 	/* Top of Upper Usable DRAM, including remap */
-	touud  = pci_read_config32(dev, TOUUD + 4);
-	touud <<= 32;
-	touud |= pci_read_config32(dev, TOUUD);
+	touud  = get_touud(dev);
 
 	/* Top of Lower Usable DRAM */
 	tolud = pci_read_config32(dev, TOLUD);
@@ -372,13 +380,32 @@
 	pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
 }
 
+static void set_above_4g_pci(const struct device *dev)
+{
+	const uint64_t touud = get_touud(dev);
+	const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
+
+	acpigen_write_scope("\\");
+	acpigen_write_name_qword("A4GB", touud);
+	acpigen_write_name_qword("A4GS", len);
+	acpigen_pop_len();
+
+	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len);
+}
+
+static void mc_gen_ssdt(const struct device *dev)
+{
+	generate_cpu_entries(dev);
+	set_above_4g_pci(dev);
+}
+
 static struct device_operations mc_ops = {
 	.read_resources         = mc_read_resources,
 	.set_resources          = pci_dev_set_resources,
 	.enable_resources       = pci_dev_enable_resources,
 	.init                   = northbridge_init,
 	.ops_pci                = &pci_dev_ops_pci,
-	.acpi_fill_ssdt		= generate_cpu_entries,
+	.acpi_fill_ssdt		= mc_gen_ssdt,
 };
 
 static const unsigned short pci_device_ids[] = {