tree 1d576b79ee595b2236652360f51e8d3f52b349c1
parent 6ef863c5c43aaccbc99c8518832e786f8cd5e9d1
author Furquan Shaikh <furquan@google.com> 1633495053 -0700
committer Furquan Shaikh <furquan@google.com> 1634659766 +0000

soc/intel/alderlake: Enable support for CSE stitching

This change enables support for stitching of BP1 and BP2 partitions
for CSE. This currently mimics what Intel FIT tool does w.r.t. adding
different components to the different partitions.

BP1:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP.
* Decomposed components from CSE FPT file: RBEP, MFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC.

BP2:
* Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP.
* Decomposed components from CSE FPT file: RBEP, FTPR, NFTP.
* Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP.

BUG=b:189177580,b:189177538

Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>