soc/intel/broadwell: Drop vboot support
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it
with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support
flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES),
drop vboot as well as ChromeOS support for all broadwell boards,
including auron, jecht and wtm2.
[1] https://issuetracker.google.com/issues/235293589
BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_GUADO -a
TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a
Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 6f0ff89..3551be1 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -8,7 +8,6 @@
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
- select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LIBGFXINIT
select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM1
@@ -44,11 +43,6 @@
if BOARD_GOOGLE_BASEBOARD_AURON
-config VBOOT
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select VBOOT_LID_SWITCH
- select VBOOT_VBNV_CMOS
-
config MAINBOARD_DIR
default "google/auron"
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index 584b88b..e011df7 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -5,7 +5,6 @@
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
- select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LIBGFXINIT
select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM1
@@ -26,9 +25,6 @@
if BOARD_GOOGLE_BASEBOARD_JECHT
-config VBOOT
- select VBOOT_VBNV_CMOS
-
config MAINBOARD_DIR
default "google/jecht"
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 9977d3b..b8b7e27 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -7,13 +7,9 @@
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
- select MAINBOARD_HAS_CHROMEOS
select MEMORY_MAPPED_TPM
select INTEL_INT15
-config VBOOT
- select VBOOT_VBNV_CMOS
-
config MAINBOARD_DIR
default "intel/wtm2"
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 2647c17..4b4df52 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -13,25 +13,6 @@
select MRC_SETTINGS_PROTECT
select REG_SCRIPT
-config BROADWELL_VBOOT_IN_BOOTBLOCK
- depends on VBOOT
- bool "Start verstage in bootblock"
- default y
- select VBOOT_STARTS_IN_BOOTBLOCK
- help
- Broadwell can either start verstage in a separate stage
- right after the bootblock has run or it can start it
- after romstage for compatibility reasons.
- Broadwell however uses a mrc.bin to initialize memory which
- needs to be located at a fixed offset. Therefore even with
- a separate verstage starting after the bootblock that same
- binary is used meaning a jump is made from RW to the RO region
- and back to the RW region after the binary is done.
-
-config VBOOT
- select VBOOT_MUST_REQUEST_DISPLAY
- select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
-
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
@@ -97,13 +78,6 @@
hex
default 0xfffa0000
-# The UEFI System Agent binary needs to be at a fixed offset in the flash
-# and can therefore only reside in the COREBOOT fmap region
-config RO_REGION_ONLY
- string
- depends on VBOOT
- default "mrc.bin"
-
endif # HAVE_MRC
config HAVE_REFCODE_BLOB