| commit | f843e0a8efcc6f0474df689a3fc4b388cfe6447b | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Tue Feb 09 17:44:07 2021 +0100 |
| committer | Patrick Georgi <pgeorgi@google.com> | Thu Feb 11 10:18:54 2021 +0000 |
| tree | 73b7c5eb058269c924c62fe63e0905acf3b3d5cf | |
| parent | b53dfc727e013ccd92095a454bac89b01d404a80 [diff] [blame] |
nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment
Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index a61036a..2dfad62 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -13,7 +13,7 @@ #define MC_INIT_STATE_G 0x5030 #define MRC_REVISION 0x5034 /* MRC Revision */ -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ +#define MC_LOCK 0x50fc /* Memory Controller Lock register */ #define GFXVTBAR 0x5400 /* Base address for IGD */ #define EDRAMBAR 0x5408 /* Base address for eDRAM */