tree 7cf7b68561cfb4e70d00f0aa6429b4fe7864c38a
parent 5304ce108e1f8fceff543543be092253cf09edb0
author Furquan Shaikh <furquan@google.com> 1617418872 -0700
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1617632131 +0000

mb/google/brya: Enable south XHCI ports 1 and 2

FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.

BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.

Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>