mb/google/brox: Add support for batteryless booting
Set PsysPL2 and PsysPL3 in addition to making adjustments
to PL2 and PL4 in order to prevent brownouts when we don't
have a battery or have an empty battery at boot time.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=flash
Able to successfully boot on a SKU1 with 45W, 60W+ adapters
and SKU2 with a 60W or higher type C adapter.
30W is still being worked on.
Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
index 7853863..be1ba08 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
@@ -5,44 +5,163 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <drivers/intel/dptf/chip.h>
+#include <ec/google/chromeec/ec.h>
#include <intelblocks/power_limit.h>
#include <soc/pci_devs.h>
WEAK_DEV_PTR(dptf_policy);
+#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
+#define SET_PL2(e, w) ((e - 27) * (w) / 100)
+
+static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries,
+ size_t *intel_idx, size_t *brox_idx)
+{
+ uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+ u8 tdp = get_cpu_tdp();
+ size_t i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+ if (mchid == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) {
+ *intel_idx = cpuid_to_adl[i].limits;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(cpuid_to_adl)) {
+ printk(BIOS_ERR, "Cannot find correct intel sku index (mchid = %u).\n", mchid);
+ return false;
+ }
+
+ for (i = 0; i < num_entries; i++) {
+ if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+ *brox_idx = i;
+ break;
+ }
+ }
+
+ if (i == num_entries) {
+ printk(BIOS_ERR, "Cannot find correct brox sku index (mchid = %u).\n", mchid);
+ return false;
+ }
+
+ return true;
+}
+
void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
{
+ const struct device *policy_dev;
+ size_t intel_idx, brox_idx;
+ struct drivers_intel_dptf_config *config;
+ struct dptf_power_limits *settings;
+ config_t *conf;
+ struct soc_power_limits_config *soc_config;
+
if (!num_entries)
return;
- const struct device *policy_dev = DEV_PTR(dptf_policy);
+ policy_dev = DEV_PTR(dptf_policy);
if (!policy_dev)
return;
- struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+ if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+ return;
- uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+ config = policy_dev->chip_info;
+ settings = &config->controls.power_limits;
+ conf = config_of_soc();
+ soc_config = &conf->power_limits_config[intel_idx];
+ settings->pl1.min_power = limits[brox_idx].pl1_min_power;
+ settings->pl1.max_power = limits[brox_idx].pl1_max_power;
+ settings->pl2.min_power = limits[brox_idx].pl2_min_power;
+ settings->pl2.max_power = limits[brox_idx].pl2_max_power;
- u8 tdp = get_cpu_tdp();
-
- for (size_t i = 0; i < num_entries; i++) {
- if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
- struct dptf_power_limits *settings = &config->controls.power_limits;
- config_t *conf = config_of_soc();
- struct soc_power_limits_config *soc_config = conf->power_limits_config;
- settings->pl1.min_power = limits[i].pl1_min_power;
- settings->pl1.max_power = limits[i].pl1_max_power;
- settings->pl2.min_power = limits[i].pl2_min_power;
- settings->pl2.max_power = limits[i].pl2_max_power;
- soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
- MILLIWATTS_TO_WATTS);
- printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
- limits[i].pl1_min_power,
- limits[i].pl1_max_power,
- limits[i].pl2_min_power,
- limits[i].pl2_max_power,
- limits[i].pl4_power);
- }
+ if (soc_config->tdp_pl2_override != 0) {
+ settings->pl2.max_power = soc_config->tdp_pl2_override * 1000;
+ settings->pl2.min_power = settings->pl2.max_power;
}
+
+ if (soc_config->tdp_pl4 == 0)
+ soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power,
+ MILLIWATTS_TO_WATTS);
+}
+
+/*
+ * Psys calculations
+ *
+ * We use the following:
+ *
+ * For USB C charger (Max Power):
+ * +-------------+-----+------+---------+-------+
+ * | Max Power(W)| TDP | PL2 | PsysPL2 | PL3/4 |
+ * +-------------+-----+------+---------+-------+
+ * | 30 | 15 | 17 | 25 | 25 | <--- not working yet
+ * | 45 | 15 | 26 | 38 | 38 |
+ * | 60 | 15 | 35 | 51 | 51 |
+ * | 110 | 15 | 55 | 94 | 96 |
+ * +-------------+-----+------+---------+-------+
+ */
+void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
+ const struct system_power_limits *sys_limits,
+ size_t num_entries,
+ const struct psys_config *config_psys)
+{
+ struct soc_power_limits_config *soc_config;
+ size_t intel_idx, brox_idx;
+ u16 volts_mv, current_ma;
+ enum usb_chg_type type;
+ u32 pl2;
+ u32 psyspl2 = 0;
+ u32 psyspl3 = 0;
+ u32 pl2_default;
+ config_t *conf;
+ u32 watts = 0;
+ int rv;
+
+ if (!num_entries)
+ return;
+
+ if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+ return;
+
+ conf = config_of_soc();
+ soc_config = &conf->power_limits_config[intel_idx];
+
+ pl2_default = DIV_ROUND_UP(limits[brox_idx].pl2_max_power, MILLIWATTS_TO_WATTS);
+
+ /* Get AC adapter power */
+ rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
+
+ if (rv == 0 && type == USB_CHG_TYPE_PD) {
+ /* Detected USB-PD. Get max value of adapter */
+ watts = ((u32)current_ma * volts_mv) / 1000000;
+ }
+ /* If battery is present and has enough charge, add discharge rate */
+ if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_battery_present_and_above_critical_threshold()) {
+ watts += 65;
+ }
+
+ /* We did not detect a battery or a Type-C charger */
+ if (watts == 0) {
+ return;
+ }
+
+ /* set psyspl2 to efficiency% of adapter rating */
+ psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
+ psyspl3 = psyspl2;
+ if (watts > 60)
+ psyspl3 += 2;
+
+ /* Limit PL2 if the adapter is with lower capability */
+ pl2 = (psyspl2 > pl2_default) ? pl2_default : SET_PL2(config_psys->efficiency, watts);
+
+ /* If PL4 > psyspl3, lower it */
+ if (soc_config->tdp_pl4 > psyspl3)
+ soc_config->tdp_pl4 = psyspl3;
+
+ /* now that we're done calculating, set everything */
+ soc_config->tdp_pl2_override = pl2;
+ soc_config->tdp_psyspl2 = psyspl2;
+ soc_config->tdp_psyspl3 = psyspl3;
}
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 424d61c..21774f8 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -133,7 +133,7 @@
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
- device generic 0 on end
+ device generic 0 alias dptf_policy on end
end
end # DTT
device ref igpu on
diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c
index b468320..86418da 100644
--- a/src/mainboard/google/brox/variants/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/brox/ramstage.c
@@ -2,17 +2,53 @@
#include <baseboard/variants.h>
#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
-const struct cpu_power_limits limits[] = {
- /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
- /* All values are for performance config as per document #686872 */
- { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
- { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
- { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+ {
+ .mchid = PCI_DID_INTEL_RPL_P_ID_3,
+ .cpu_tdp = 15,
+ .pl1_min_power = 6000,
+ .pl1_max_power = 15000,
+ .pl2_min_power = 55000,
+ .pl2_max_power = 55000,
+ .pl4_power = 114000
+ },
+ {
+ .mchid = PCI_DID_INTEL_RPL_P_ID_4,
+ .cpu_tdp = 15,
+ .pl1_min_power = 6000,
+ .pl1_max_power = 15000,
+ .pl2_min_power = 55000,
+ .pl2_max_power = 55000,
+ .pl4_power = 114000
+ },
};
-void variant_devtree_update(void)
+const struct system_power_limits sys_limits[] = {
+ /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 60 },
+ { PCI_DID_INTEL_RPL_P_ID_4, 15, 60 },
+};
+
+const struct psys_config psys_config = {
+ .efficiency = 86,
+};
+
+void __weak variant_devtree_update(void)
{
- size_t total_entries = ARRAY_SIZE(limits);
- variant_update_power_limits(limits, total_entries);
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+ const struct cpu_power_limits *limits = performance_efficient_limits;
+ size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+ variant_update_power_limits(limits, limits_size);
+ variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config);
}