tree df0963a616bb3455261c293fc45bc51d7b4e05e9
parent 949bce5adf377bf82734e98d74ff3896f08003cd
author Felix Held <felix-coreboot@felixheld.de> 1677864555 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1678123192 +0000

soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define

Picasso and newer don't implement the P_CNT register to control the CPU
duty cycle and also trap the C state control IO addresses directly in
the CPU, so those won't reach the FCH. This register is unused in the
Picasso code and not even defined any more in the Cezanne PPR. The
Picasso PPR does define this register, but since it's useless and might
even just be a leftover form a pre-Zen CPU generation, drop the define.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>