soc/intel/quark: Clean up debug output levels
Change the debug output levels for quark:
* Remove excess debug output
* Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c
TEST=Build and run on Galileo Gen2
Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c
index 90adc34..960b53f 100644
--- a/src/soc/intel/quark/acpi.c
+++ b/src/soc/intel/quark/acpi.c
@@ -97,9 +97,9 @@
fadt->x_gpe0_blk.addrh = 0;
/* Display the base registers */
- printk(BIOS_DEBUG, "FADT:\n");
- printk(BIOS_DEBUG, " 0x%08x: GPE0_BASE\n", gpe0_base);
- printk(BIOS_DEBUG, " 0x%08x: PMBASE\n", pmbase);
- printk(BIOS_DEBUG, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
+ printk(BIOS_SPEW, "FADT:\n");
+ printk(BIOS_SPEW, " 0x%08x: GPE0_BASE\n", gpe0_base);
+ printk(BIOS_SPEW, " 0x%08x: PMBASE\n", pmbase);
+ printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
}
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 29b6152..77fb1fd 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -134,10 +134,8 @@
static void chip_enable_dev(device_t dev)
{
- const char *type_name = dev_path_name(dev->path.type);
/* Set the operations if it is a special bus type */
- printk(BIOS_DEBUG, "type: %s\n", type_name);
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
}
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index e5c0f0b..3d530b9 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -94,7 +94,7 @@
offset = (index - MTRR_PHYS_BASE(0))
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
else {
- printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
+ printk(BIOS_SPEW, "index: 0x%08lx\n", index);
die("Invalid MTRR index specified!\n");
}
return offset;
diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c
index f2adc18..24dcf23 100644
--- a/src/soc/intel/quark/romstage/pcie.c
+++ b/src/soc/intel/quark/romstage/pcie.c
@@ -100,10 +100,7 @@
void pcie_init(void)
{
/* Initialize the PCIe bridges */
- printk(BIOS_DEBUG, "Initializing PCIe controllers\n");
reg_script_run(pcie_init_script);
- printk(BIOS_DEBUG, "Initializing PCIe bus 0\n");
reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script);
- printk(BIOS_DEBUG, "Initializing PCIe bus 1\n");
reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script);
}
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 9ee4135..e774993 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -18,7 +18,6 @@
#include <arch/early_variables.h>
#include <console/console.h>
#include <fsp/util.h>
-#include <lib.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
@@ -53,7 +52,6 @@
/* Determine if the shadow ROM is enabled */
data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
QNC_MSG_FSBIC_REG_HMISC);
- printk(BIOS_DEBUG, "0x%08x: HMISC\n", data);
if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM))
!= (ESEG_RD_DRAM | FSEG_RD_DRAM)) {
@@ -62,7 +60,4 @@
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
QNC_MSG_FSBIC_REG_HMISC, data);
}
-
- /* Display the DRAM data */
- hexdump((void *)0x000ffff0, 0x10);
}