commit f731132fa053aebc064cd3d80bb9e063915bca67
author David Wu <david_wu@quanta.corp-partner.google.com> Fri Jul 28 11:08:56 2023 +0800
committer Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tue Aug 08 16:03:04 2023 +0000
tree 99b1eac038b3906db7bffda68343a7857b90b6b4
parent 9faf74ca96e7796a091a514d6fbad8a664514f72

mb/google/brask/var/kuldax: Set power limit values for RPL SKUs

Add the RPL CPU power limits and system power limits based on
the suggestion of the thermal team for RPL SKUs.

The PL4 value suggested by the thermal team which is different from the reference document 686872.

BUG=b:292471206
BRANCH=firmware-brya-14505.B
TEST=built and booted into OS.

Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>

src/mainboard/google/brya/variants/kuldax/overridetree.cb

diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
index 6168b2f..41a9e28 100644
--- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
@@ -51,6 +51,12 @@
 		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 100,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf

src/mainboard/google/brya/variants/kuldax/ramstage.c

diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c
index 5a71237..2062383 100644
--- a/src/mainboard/google/brya/variants/kuldax/ramstage.c
+++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c
@@ -16,6 +16,9 @@
 	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000,  55000,  55000, 123000 },
 	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000,  64000,  64000, 140000 },
 	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000,  64000,  64000, 140000 },
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000,  55000,  55000, 100000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000,  55000,  55000, 100000 },
 };
 
 const struct system_power_limits sys_limits[] = {
@@ -25,6 +28,9 @@
 	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
 	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
 	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
 };
 
 const struct system_power_limits revise_sys_limits[] = {
@@ -34,6 +40,9 @@
 	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 225 },
 	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 225 },
 	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 225 },
+	{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
 };
 
 /*