S3 code in coreboot public folder.
1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.
Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 15efe12..2647814 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -745,20 +745,46 @@
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
}
-static void domain_enable_resources(device_t dev) {
+extern u8 acpi_slp_type;
+
+static void domain_enable_resources(device_t dev)
+{
u32 val;
#if CONFIG_AMD_SB_CIMX
+ #if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type != 3) {
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+ } else {
+ sb_After_Pci_Restore_Init();
+ }
+ #else
sb_After_Pci_Init();
sb_Mid_Post_Init();
+ #endif
#endif
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
- val = agesawrapper_amdinitmid();
- if (val) {
- printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type != 3) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitmid ");
+ val = agesawrapper_amdinitmid ();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
}
+#else
+ printk(BIOS_DEBUG, "agesawrapper_amdinitmid ");
+ val = agesawrapper_amdinitmid ();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+#endif
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
}
@@ -788,24 +814,41 @@
pci_dev_set_resources(dev);
}
-static void cpu_bus_init(device_t dev) {
- struct device_path cpu_path;
+static u32 cpu_bus_scan(device_t dev, u32 max)
+{
device_t cpu;
- int apic_id;
+ struct device_path cpu_path;
+ int apic_id, cores_found;
- initialize_cpus(dev->link_list);
+ /* There is only one node for fam14, but there may be multiple cores. */
+ cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ if (!cpu)
+ printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18);
- /* Build the AP cpu device path(s) */
- for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) {
+ cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3;
+ printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found);
+
+
+ for (apic_id = 0; apic_id <= cores_found; apic_id++) {
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id;
- cpu = alloc_dev(dev->link_list, &cpu_path);
- if (!cpu)
- return;
- cpu->enabled = 1;
- cpu->path.apic.node_id = 0;
- cpu->path.apic.core_id = apic_id;
+ cpu = alloc_find_dev(dev->link_list, &cpu_path);
+ if (cpu) {
+ cpu->enabled = 1;
+ cpu->path.apic.node_id = 0;
+ cpu->path.apic.core_id = apic_id;
+ printk(BIOS_DEBUG, "CPU: %s %s\n",
+ dev_path(cpu), cpu->enabled?"enabled":"disabled");
+ } else {
+ cpu->enabled = 0;
+ }
}
+ return max;
+}
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
}
/* North Bridge Structures */
@@ -844,7 +887,7 @@
.set_resources = cpu_bus_set_resources,
.enable_resources = NULL,
.init = cpu_bus_init,
- .scan_bus = NULL,
+ .scan_bus = cpu_bus_scan,
};
static void root_complex_enable_dev(struct device *dev) {