nb/intel/x4x/rcven.c: Fix programming coarse offset
This fixes some bitwise logic errors that caused the coarse offset not
to be programmed.
This fixes a regression introduced by 6d7a8c
"nb/intel/x4x/raminit: Rework receive enable calibration"
where the coarse offset doesn't get programmed anymore.
TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable
delays are close but above and below the edge of a coarse delay setting.
Change-Id: I41869815f782a2ea1178bdea006e3a7587441323
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 23f8d52..cc45aa9 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -365,8 +365,9 @@
"medium: %d; tap: %d\n",
channel, lane, reg8, timing[lane].medium,
timing[lane].tap);
- MCHBAR16(0x400 * channel + 0x5fa) &=
- ~(3 << (lane * 2)) | (reg8 << (lane * 2));
+ MCHBAR16(0x400 * channel + 0x5fa) =
+ (MCHBAR16(0x400 * channel + 0x5fa) &
+ ~(3 << (lane * 2))) | (reg8 << (lane * 2));
}
/* simply use timing[0] to program mincoarse */
timing[0].coarse = mincoarse;